HYS64T256020HU Datasheet, PDF(7/61 Page) Qimonda AG – 240-Pin Unbuffered DDR2 SDRAM Modules

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HYS64T256020HU Datasheet, PDF (7/61 Pages) Qimonda AG – 240-Pin Unbuffered DDR2 SDRAM Modules

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Internet Data Sheet

HYS[64/72]T256xxxHUâ[3/â¦/5]âA

Unbuffered DDR2 SDRAM Modules

2

Pin Configurations

2.1

Pin Configuration

The pin configuration of the Unbuffered DDR2 SDRAM DIMM is listed by function in Table 7 (240 pins). The abbreviations used

in columns Pin and Buffer Type are explained in Table 8 and Table 9 respectively. The pin numbering is depicted in Figure 1

for non-ECC modules (Ã64) and Figure 2 for ECC modules (Ã72).

Ball No.

Name

Clock Signals

185

137

220

186

138

221

52

171

CK0

CK1

CK2

CK0

CK1

CK2

CKE0

CKE1

NC

Control Signals

193

S0#

76

S1#

NC

192

74

73

Address Signals

71

190

54

RAS

CAS

WE

BA0

BA1

BA2

NC

Pin

Type

I

I

I

I

I

I

I

I

NC

I

I

NC

I

I

I

I

I

I

NC

Buffer

Type

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

â

SSTL

SSTL

â

SSTL

SSTL

SSTL

SSTL

SSTL

SSTL

â

Function

TABLE 7

Pin Configuration of UDIMM

Clock Signals 2:0, Complement Clock Signals 2:0

Clock Enable Rank 1:0

Note: 2 Ranks module

Not Connected

Note: 1 Rank module

Chip Select Rank 1:0

Note: 2 Ranks module

Not Connected

Note: 1 Rank module

Row Address Strobe

Column Address Strobe

Write Enable

Bank Address Bus 1:0

Bank Address Bus 2

Not Connected

Rev. 1.32, 2006-09

7

03062006-5RK8-1X8J

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