HYS64T256020HU Datasheet, PDF (44/61 Pages) Qimonda AG – 240-Pin Unbuffered DDR2 SDRAM Modules

Internet Data Sheet
HYS[64/72]T256xxxHU–[3/…/5]–A
Unbuffered DDR2 SDRAM Modules
Product Type
Organization
Label Code
JEDEC SPD Revision
Byte#
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
Description
t_RAS.MIN [ns]
Module Density per Rank
t_AS.MIN and t_CS.MIN [ns]
t_AH.MIN and t_CH.MIN [ns]
t_DS.MIN [ns]
t_DH.MIN [ns]
t_WR.MIN [ns]
t_WTR.MIN [ns]
t_RTP.MIN [ns]
Analysis Characteristics
t_RC and t_RFC Extension
t_RC.MIN [ns]
t_RFC.MIN [ns]
t_CK.MAX [ns]
t_DQSQ.MAX [ns]
t_QHS.MAX [ns]
PLL Relock Time
T_CASE.MAX Delta / ∆T_4R4W Delta
Psi(T-A) DRAM
∆T₀ (DT0)
∆T_2N (DT2N, UDIMM) or ∆T_2Q (DT2Q, RDIMM)
∆T_2P (DT2P)
∆T_3N (DT3N)
∆T_3P.fast (DT3P fast)
∆T_3P.slow (DT3P slow)
∆T_4R (DT4R) / ∆T_4R4W Sign (DT4R4W)
∆T_5B (DT5B)
∆T₇ (DT7)
Psi(ca) PLL
Psi(ca) REG
∆T_PLL (DTPLL)
∆T_REG (DTREG) / Toggle Rate
SPD Revision
HYS64T256020HU–3S–A HYS72T256020HU–3S–A
2 GByte
2 GByte
×64
×72
2 Ranks (×8)
2 Ranks (×8)
PC2–5300U–555
PC2–5300E–555
Rev. 1.2
Rev. 1.2
HEX
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
50
58
37
32
21
24
23
17
4A
21
28
00
00
00
00
12
HEX
2D
01
20
27
10
17
3C
1E
1E
00
06
3C
7F
80
18
22
00
50
58
37
32
21
24
23
17
4A
21
28
00
00
00
00
12
Rev. 1.32, 2006-09
44
03062006-5RK8-1X8J