HYS64D64300GU-5-B Datasheet, PDF (5/42 Pages) Qimonda AG – 42184-Pin Unbuffered Double-Data-Rate Memory Modules

Internet Data Sheet
HYS[64/72]D[32/64/128]xxx[G/H]U–[5/6]–B
Unbuffered DDR SDRAM Modules
2
Pin Configuration
The pin configuration of the Unbuffered DDR SDRAM DIMM
is listed by function in Table 3 (184 pins). The abbreviations
used in columns Pin and Buffer Type are explained in Table 4
and Table 5 respectively. The pin numbering is depicted in
Figure 1.
Pin#
Name
Clock Signals
137
CK0
NC
16
CK1
76
CK2
138
CK0
NC
17
CK1
75
CK2
21
CKE0
111
CKE1
NC
Control Signals
157
S0
158
S1
NC
154
RAS
65
CAS
63
WE
Pin
Type
I
NC
I
I
I
NC
I
I
I
I
NC
I
I
NC
I
I
I
Buffer
Type
SSTL
–
SSTL
SSTL
SSTL
–
SSTL
SSTL
SSTL
SSTL
–
SSTL
SSTL
–
SSTL
SSTL
SSTL
Function
TABLE 3
Pin Configuration of UDIMM
Clock Signals 2:0
Complement Clock Signals 2:0
Clock Enable Rank 0
Clock Enable Rank 1
Note: 2-rank module
Note: 1-rank module
Chip Select Rank 0
Chip Select Rank 1
Note: 2-rank module
Note: 1-rank module
Row Address Strobe
Column Address Strobe
Write Enable
Rev. 1.22, 2007-01
5
03292006-CXBY-V2JX