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HYS64D64300GU-5-B Datasheet, PDF (3/42 Pages) Qimonda AG – 42184-Pin Unbuffered Double-Data-Rate Memory Modules | |||
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Internet Data Sheet
1
Overview
HYS[64/72]D[32/64/128]xxx[G/H]Uâ[5/6]âB
Unbuffered DDR SDRAM Modules
This chapter contains features and the description.
1.1
Features
⢠184-Pin Unbuffered Double-Data-Rate Memory Modules
(ECC and non-parity) for PC and Workstation main
memory applications
⢠One rank 32M à 64, 64M x 64, 64M Ã72 and two ranks
128M Ã 64, 128M Ã72 organization
⢠standard Double Data Rate Synchronous DRAMs Single
+2.5V (± 0.2V) power supply
⢠Built with 512-Mbit in P-TSOPII-66 package
⢠Programmable CAS Latency, Burst Length, and Wrap
Sequence (Sequential & Interleave)
⢠Auto Refresh (CBR) and Self Refresh
⢠All inputs and outputs SSTL_2 compatible
⢠Serial Presence Detect with E2PROM
⢠JEDEC standard MO-206 form factor:
133.35 mm à 31.75 mm à 4.00 mm max.
⢠Standard reference layout
⢠Gold plated contacts
⢠DDR400 speed grade supported
⢠Lead-free
Part Number Speed Code
Speed Grade
Max. Clock Frequency
Component
Module
@CL3
@CL2.5
@CL2
fCK3
fCK2.5
fCK2
â5
DDR400B
PC3200 - 3033
200
166
133
TABLE 1
Performance for â5 and â6
â6
Unit
DDR333B
PC2700 - 2533
166
166
133
â
â
MHz
MHz
MHz
1.2
Description
The Qimonda HYS64D32301[G/H]Uâ5âB, HYS[64/72]D64xxx[G/H]Uâ
[5/6]âB and HYS[64/72]D128xxx[G/H]Uâ[5/6]âB are industry standard
184-Pin Unbuffered Double-Data-Rate Memory Modules (UDIMM)
organized as 32M Ã 64M (256 MB), 64M Ã64 (512 MB),
128M Ã64 (1 GB) for non-parity and 64M Ã72 (512 MB),
128M Ã72 (1 GB) for ECC main memory applications. The
memory array is designed with 512Mbit Double Data Rate
Synchronous DRAMs. A variety of decoupling capacitors are
mounted on the printed circuit board. The DIMMs feature
serial presence detect (SPD) based on a serial E2PROM
device using the 2-pin I2C protocol. The first 128 bytes are
programmed with configuration data and the second
128 bytes are available to the customer.
Rev. 1.22, 2007-01
3
03292006-CXBY-V2JX
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