HYS64T32X00HDL Datasheet, PDF (31/70 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Symbol Parameter / Condition
Values
Unit
Note
Min.
Max.
t_AOFPD
ODT turn-off (Power-Down Modes)
t_AC.MIN + 2 ns 2.5 t_{CK +} t_AC.MAX + 1 ns ns
1)
t_ANPD
ODT to Power Down Mode Entry Latency
3
—
nCK
1)
t_AXPD
ODT Power Down Exit Latency
8
—
nCK
1)
1) New units, 't_CK.AVG' and 'nCK', are introduced in DDR2-667 and DDR2-800. Unit 't_CK.AVG' represents the actual t_CK.AVG of the input clock
under operation. Unit 'nCK' represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, 't_CK' is used for both concepts. Example: t_XP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command may
be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 × t_CK.AVG+ t_{EPR.2PER(MIN)}.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-667/800, t_AOND is 2
clock cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD. Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-667/800,if t_CK.AVG =
3 ns is assumed, t_AOFD= 1.5 ns (0.5 × 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT
LOW and by counting the actual input clock edge.
Symbol
TABLE 21
ODT AC Character. and Operating Conditions for DDR2-533 & DDR2-400
Parameter / Condition
Values
Unit
Note
Min.
Max.
t_AOND
t_AON
ODT turn-on delay
ODT turn-on
2
t_AC.MIN
2
t_AC.MAX + 1 ns
t_CK
ns
1)
t_AONPD
ODT turn-on (Power-Down Modes)
t_AC.MIN + 2 ns 2 t_{CK +} t_AC.MAX + 1 ns
ns
t_AOFD
t_AOF
ODT turn-off delay
ODT turn-off
2.5
t_AC.MIN
2.5
t_AC.MAX + 0.6 ns
t_CK
ns
2)
t_AOFPD
ODT turn-off (Power-Down Modes)
t_AC.MIN + 2 ns 2.5 t_{CK +} t_AC.MAX + 1 ns ns
t_ANPD
ODT to Power Down Mode Entry Latency
3
—
t_CK
t_AXPD
ODT Power Down Exit Latency
8
—
t_CK
1) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-400/533, t_AOND is
10 ns (= 2 x 5 ns) after the clock edge that registered a first ODT HIGH if t_CK = 5 ns.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD. Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-400/533, t_AOFD is
12.5 ns (= 2.5 x 5 ns) after the clock edge that registered a first ODT HIGH if t_CK = 5 ns.
Rev. 1.1, 2006-10
31
03292006-5LTN-QML0