HYS64T32X00HDL Datasheet, PDF (23/70 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2–667
Min.
Max.
Unit
Note^{1)2)3)4)5)6)7)}
8)
Exit precharge power-down to any valid
t_XP
2
command (other than NOP or Deselect)
—
nCK
Exit power down to read command
Exit active power-down mode to read command
(slow exit, lower power)
CKE minimum pulse width ( high and low pulse
width)
t_XARD
t_XARDS
t_CKE
2
—
7 – AL
—
3
—
nCK
nCK
nCK
31)
Mode register set command cycle time
t_MRD
2
MRS command to ODT update delay
t_MOD
0
—
nCK
12
ns
1)
OCD drive mode output delay
t_OIT
0
12
ns
1)
Minimum time clocks remain ON after CKE
t_DELAY
t_IS + t_{CK .AVG} + ––
ns
asynchronously drops LOW
t_IH
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V. See notes ^5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT.
8) New units, ‘t_CK.AVG‘ and ‘nCK‘, are introduced in DDR2–667 and DDR2–800. Unit ‘t_CK.AVG‘ represents the actual t_CK.AVG of the input clock
under operation. Unit ‘nCK‘ represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2–400 and
DDR2–533, ‘t_CK‘ is used for both concepts. Example: t_XP = 2 [nCK] means; if Power Down exit is registered at Tm, an Active command
may be registered at Tm + 2, even if (Tm + 2 - Tm) is 2 x t_CK.AVG + t_{ERR.2PER(Min)}.
9) When the device is operated with input clock jitter, this parameter needs to be derated by the actual t_ERR(6-10per) of the input clock. (output
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has t_{ERR(6-10PER).MIN} = – 272
ps and t_{ERR(6- 10PER).MAX} = + 293 ps, then t_{DQSCK.MIN(DERATED)} = t_DQSCK.MIN – t_{ERR(6-10PER).MAX} = – 400 ps – 293 ps = – 693 ps and
t_{DQSCK.MAX(DERATED)} = t_DQSCK.MAX – t_{ERR(6-10PER).MIN} = 400 ps + 272 ps = + 672 ps. Similarly, t_LZ.DQ for DDR2–667 derates to t_{LZ.DQ.MIN(DERATED)}
= - 900 ps – 293 ps = – 1193 ps and t_{LZ.DQ.MAX(DERATED)} = 450 ps + 272 ps = + 722 ps. (Caution on the MIN/MAX usage!)
10) Input clock jitter spec parameter. These parameters are referred to as 'input clock jitter spec parameters' and these parameters apply to
DDR2–667 and DDR2–800 only. The jitter specified is a random jitter meeting a Gaussian distribution.
11) These parameters are specified per their average values, however it is understood that the relationship between the average timing and
the absolute instantaneous timing holds all the times (min. and max of SPEC values are to be used for calculations ).
12) Input waveform timing t_DS with differential data strobe enabled MR[bit10] = 0, is referenced from the input signal crossing at the V_IH.AC level
to the differential data strobe crosspoint for a rising signal, and from the input signal crossing at the V_IL.AC level to the differential data strobe
crosspoint for a falling signal applied to the device under test. DQS, DQS signals must be monotonic between V_il(DC)MAX and V_ih(DC)MIN. See
Figure 3.
13) If t_DS or t_DH is violated, data corruption may occur and the data must be re-written with valid data before a valid READ can be executed.
14) These parameters are measured from a data signal ((L/U)DM, (L/U)DQ0, (L/U)DQ1, etc.) transition edge to its respective data strobe signal
((L/U/R)DQS / DQS) crossing.
15) Input waveform timing t_DH with differential data strobe enabled MR[bit10] = 0, is referenced from the differential data strobe crosspoint to
the input signal crossing at the V_IH.DC level for a falling signal and from the differential data strobe crosspoint to the input signal crossing
at the V_IL.DC level for a rising signal applied to the device under test. DQS, DQS signals must be monotonic between V_IL.DC.MAX and
V_IH.DC.MIN. See Figure 3.
16) t_HZ and t_LZ transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
which specifies when the device output is no longer driving (t_HZ), or begins driving (t_LZ) .
17) t_DQSQ: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
Rev. 1.1, 2006-10
23
03292006-5LTN-QML0