HYS64T32X00HDL Datasheet, PDF (27/70 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
Parameter
Symbol
DDR2–533
Min.
Max.
Unit
Note^1)2)3)4)5)
6)7)
Average periodic refresh Interval
t_REFI
—
—
Auto-Refresh to Active/Auto-Refresh
t_RFC
105
command period
7.8
µs
14)15)
3.9
µs
16)18)
—
ns
17)
Precharge-All (4 banks) command period
Precharge-All (8 banks) command period
Read preamble
Read postamble
Active bank A to Active bank B command
period
t_RP
t_RP
t_RPRE
t_RPST
t_RRD
t_RP + 1t_CK
15 + 1t_CK
0.9
0.40
7.5
10
—
—
1.1
0.60
—
—
ns
ns
t_CK
14)
t_CK
14)
ns
14)18)
ns
16)20)
Internal Read to Precharge command delay
Write preamble
Write postamble
Write recovery time for write without Auto-
Precharge
Write recovery time for write with Auto-
Precharge
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
Exit active power-down mode to Read
command (slow exit, lower power)
t_RTP
t_WPRE
t_WPST
t_WR
WR
t_WTR
t_XARD
t_XARDS
7.5
0.25 x t_CK
0.40
15
t_WR/t_CK
7.5
2
6 – AL
—
—
0.60
—
—
—
—
—
ns
t_CK
t_CK
19)
ns
t_CK
20)
ns
21)
t_CK
22)
t_CK
22)
Exit precharge power-down to any valid
t_XP
2
command (other than NOP or Deselect)
—
t_CK
Exit Self-Refresh to non-Read command
t_XSNR
t_RFC +10
—
ns
Exit Self-Refresh to Read command
t_XSRD
200
—
t_CK
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1 V; V_DD = 1.8 V ±0.1 V. See notes ^5)6)7)8)
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS/ RDQS,
input reference level is the crosspoint when in differential strobe mode.
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT.
8) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t_CL and t_CH).
Rev. 1.1, 2006-10
27
03292006-5LTN-QML0