HYS64T32X00HDL Datasheet, PDF (25/70 Pages) Qimonda AG – 200 Pin Small-Outlined DDR2 SDRAMs Modules

Internet Data Sheet
HYS64T[32/64/128]xxxHDL-[25F/2.5/3/3S/3.7/5]-B
SO-DIMM DDR2 SDRAM Module
FIGURE 2
Method for calculating transitions and endpoint
W+=
W536 7 H QG SRLQW
92+ [P9 
92+ [P9 
92/ [P9 
92/ [P9 
7 7
W+=W536 7 HQG SRLQ W  77 
977[P9
977[P9
977[P 9
977[P9
W/=
W53 5(EHJLQSRLQW
7 7
W/=W535( E HJLQ SRLQ W  7 7 
'46
'46 
FIGURE 3
Differential input waveform timing - t_DS and t_DS
W'6 W'+
W'6  W'+
9_' _{'4 }
9_,_+DF _PLQ 
9_,_+GF _PLQ 
9₅ _()GF
9_,_/GF _PD[ 
9_,_/DF _PD[ 
9₆ _6
FIGURE 4
Differential input waveform timing - t_lS and t_lH
&.
&.
W,6  W,+ 
W,6 W,+ 
9_' _{'4 }
9_,_{+DF }PLQ
9_,_{+GF }PLQ
9₅ _()GF
9_,_{/GF }PD[ 
9_,_{/DF }PD[ 
9₆ _6
Rev. 1.1, 2006-10
25
03292006-5LTN-QML0