HYS72T64000HP-25F Datasheet, PDF (27/65 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T[64/128/256]xxxHP–[25F/2.5/3/3S/3.7]–B
240-Pin Registered DDR2 SDRAM
13) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ T_CASE ≤ 85 °C
16) 85 °C < T_CASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The t_RRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the t_WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum t_WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing t_XARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the t_WR timing parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded
up to the next integer value. t_DAL = WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
This chapter describes the ODT AC electrical characteristics.
Symbol
TABLE 18
ODT AC Characteristics and Operating Conditions for DDR2-667 & DDR2-800
Parameter / Condition
Values
Unit
Note
Min.
Max.
t_AOND
ODT turn-on delay
2
2
n_CK
1)
t_AON
ODT turn-on
t_AC.MIN
t_AC.MAX + 0.7 ns
ns
1)2)
t_AONPD
ODT turn-on (Power-Down Modes)
t_AC.MIN + 2 ns 2 t_{CK +} t_AC.MAX + 1 ns
ns
1)
t_AOFD
ODT turn-off delay
2.5
2.5
n_CK
1)
t_AOF
ODT turn-off
t_AC.MIN
t_AC.MAX + 0.6 ns
ns
1)3)
t_AOFPD
ODT turn-off (Power-Down Modes)
t_AC.MIN + 2 ns 2.5 t_{CK +} t_AC.MAX + 1 ns ns
1)
t_ANPD
ODT to Power Down Mode Entry Latency
3
—
n_CK
1)
t_AXPD
ODT Power Down Exit Latency
8
—
n_CK
1)
1) New units, “t_CK.AVG” and “n_CK”, are introduced in DDR2-667 and DDR2-800. Unit “t_CK.AVG” represents the actual t_CK.AVG of the input clock
under operation. Unit “n_CK” represents one clock cycle of the input clock, counting the actual clock edges. Note that in DDR2-400 and
DDR2-533, “t_CK” is used for both concepts. Example: t_XP = 2 [n_CK] means; if Power Down exit is registered at T_m, an Active command may
be registered at T_m + 2, even if (T_m + 2 - T_m) is 2 x t_CK.AVG + t_{ERR.2PER(Min)}.
2) ODT turn on time min is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when the
ODT resistance is fully on. Both are measured from t_AOND, which is interpreted differently per speed bin. For DDR2-667/800, t_AOND is 2 clock
cycles after the clock edge that registered a first ODT HIGH counting the actual input clock edges.
3) ODT turn off time min is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD, which is interpreted differently per speed bin. For DDR2-667/800, if t_CK(avg) = 3 ns is assumed, t_AOFD is 1.5
ns (= 0.5 x 3 ns) after the second trailing clock edge counting from the clock edge that registered a first ODT LOW and by counting the
actual input clock edges.
Rev. 1.1, 2007-03
27
03292006-EO3M-LEK7