HYS72T64301HP Datasheet, PDF(26/42 Page) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

English

English German Russian Spanish Italian Polish Chinese Japanese Korean French Portuguese	Language :

HYS72T64301HP Datasheet, PDF (26/42 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules

◁

Internet Data Sheet

HYS72T64301HPâ[3S/3.7]âA

Registered DDR2 SDRAM Modules

3.4

Currents Specifications and Conditions

This chapter describes the Specifications and Conditions.

Parameter

TABLE 19

IDD Measurement Conditions

Symbol Note1)2)

3)4)5)6)

Operating Current 0

IDD0

One bank Active - Precharge; tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN, CKE is HIGH, CS is HIGH between

valid commands. Address and control inputs are SWITCHING, Databus inputs are SWITCHING.

Operating Current 1

IDD1

One bank Active - Read - Precharge; IOUT = 0 mA, BL = 4, tCK = tCK.MIN, tRC = tRC.MIN, tRAS = tRAS.MIN,

tRCD = tRCD.MIN, AL = 0, CL = CLMIN; CKE is HIGH, CS is HIGH between valid commands. Address and

control inputs are SWITCHING, Databus inputs are SWITCHING.

Precharge Standby Current

IDD2N

All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are SWITCHING,

Data bus inputs are SWITCHING.

Precharge Power-Down Current

Other control and address inputs are STABLE, Data bus inputs are FLOATING.

IDD2P

Precharge Quiet Standby Current

IDD2Q

All banks idle; CS is HIGH; CKE is HIGH; tCK = tCK.MIN; Other control and address inputs are STABLE,

Data bus inputs are FLOATING.

Active Standby Current

IDD3N

Burst Read: All banks open; Continuous burst reads; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;

tRAS = tRAS.MAX, tRP = tRP.MIN; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING; IOUT = 0 mA.

Active Power-Down Current

IDD3P(0) â

All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to LOW (Fast Power-down Exit);

Active Power-Down Current

IDD3P(1) â

All banks open; tCK = tCK.MIN, CKE is LOW; Other control and address inputs are STABLE, Data bus inputs

are FLOATING. MRS A12 bit is set to HIGH (Slow Power-down Exit);

Operating Current

IDD4W

Burst Write: All banks open; Continuous burst writes; BL = 4; AL = 0, CL = CLMIN; tCK = tCK.MIN;

tRAS = tRAS.MAX., tRP = tRP.MAX; CKE is HIGH, CS is HIGH between valid commands. Address inputs are

SWITCHING; Data Bus inputs are SWITCHING;

Burst Refresh Current

IDD5B

tCK = tCK.MIN., Refresh command every tRFC = tRFC.MIN interval, CKE is HIGH, CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Distributed Refresh Current

IDD5D

tCK = tCK.MIN., Refresh command every tRFC = tREFI interval, CKE is LOW and CS is HIGH between valid

commands, Other control and address inputs are SWITCHING, Data bus inputs are SWITCHING.

Rev. 1.0, 2006-10

09152006-R5MQ-5KS2

▷