 English |
|
|
|
|
|
|
|
| HYS72T64301HP Datasheet, PDF (21/42 Pages) Qimonda AG – 240-Pin Registered DDR2 SDRAM Modules | |||
| |||
| ◁ |
Internet Data Sheet
HYS72T64301HPâ[3S/3.7]âA
Registered DDR2 SDRAM Modules
FIGURE 2
Method for calculating transitions and endpoint
tHZ
tRPST end point
VOH - x mV
VOH - 2x mV
VOL + 2x mV
VOL + x mV
T1 T2
tHZ,tRPST end point = 2*T1-T2
VTT + 2x mV
VTT + x mV
VTT - x mV
VTT - 2x mV
tLZ
tRPRE begin point
T1 T2
tLZ,tRPRE begin point = 2*T1-T2
DQS
DQS
FIGURE 3
Differential input waveform timing - tDS and tDS
tDS tDH
tDS tDH
VDDQ
VIH(ac) min
VIH(dc) min
V REF(dc)
VIL(dc) max
VIL(ac) max
VSS
FIGURE 4
Differential input waveform timing - tlS and tlH
CK
CK
tIS tIH
tIS tIH
VDDQ
VIH(ac) min
VIH(dc) min
VREF(dc)
VIL(dc) max
VIL(ac) max
VSS
Rev. 1.0, 2006-10
21
09152006-R5MQ-5KS2
|
▷ |
German
Russian
Spanish
Italian
Polish
Chinese
Japanese
Korean
French
Portuguese