HYS64T32X00EDL_1 Datasheet, PDF (22/79 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules

Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol
Mode register set command cycle time t_MRD
OCD drive mode output delay
t_OIT
Data output hold time from DQS
t_QH
Data hold skew factor
t_QHS
Average periodic refresh Interval
t_REFI
Auto-Refresh to Active/Auto-Refresh
t_RFC
command period
Precharge-All (4 banks) command period t_RP
Precharge-All (8 banks) command period t_RP
Read preamble
t_RPRE
Read postamble
t_RPST
Active bank A to Active bank B command t_RRD
period
Active bank A to Active bank B command t_RRD
period
Internal Read to Precharge command t_RTP
delay
Write preamble
Write postamble
Write recovery time for write without
Auto-Precharge
t_WPRE
t_WPST
t_WR
Internal Write to Read command delay
Exit power down to any valid command
(other than NOP or Deselect)
t_WTR
t_XARD
Exit active power-down mode to Read t_XARDS
command (slow exit, lower power)
Exit precharge power-down to any valid t_XP
command (other than NOP or Deselect)
Exit Self-Refresh to non-Read command t_XSNR
Exit Self-Refresh to Read command
t_XSRD
Write recovery time for write with Auto- WR
Precharge
DDR2–533
Min.
2
0
t_HP –t_QHS
—
—
105
t_RP
t_RP + 1 × t_CK
0.9
0.40
7.5
10
7.5
0.25
0.40
15
7.5
2
6 – AL
2
t_RFC +10
200
t_WR/t_CK
Max.
—
12
—
400
7.8
—
—
—
1.1
0.60
—
—
—
—
0.60
—
—
—
—
—
—
—
Unit
t_CK
ns
ps
µs
ns
ns
ns
t_CK
t_CK
ns
ns
ns
t_CK
t_CK
ns
ns
t_CK
t_CK
t_CK
ns
t_CK
t_CK
Notes^2)3)4)5)6)
7)
14)15)
17)
14)
14)
14)18)
16)22)
19)
20)
21)
21)
22)
1) For details and notes see the relevant Qimonda component data sheet
2) V_DDQ = 1.8 V ± 0.1V; V_DD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
4) Timings are guaranteed with CK/CK differential Slew Rate of 2.0 V/ns. For DQS signals timings are guaranteed with a differential Slew
Rate of 2.0 V/ns in differential strobe mode and a Slew Rate of 1 V/ns in single ended mode.
5) The CK / CK input reference level (for timing reference to CK / CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode. component
6) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ is recognized as low.
7) The output timing reference voltage level is V_TT. component datasheet
8) For each of the terms, if not already an integer, round to the next highest integer. t_CK refers to the application clock period. WR refers to
the WR parameter stored in the MR.
Rev. 1.13, 2007-10
22
08212006-PKYN-2H1B