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HYS64T32X00EDL_1 Datasheet, PDF (17/79 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules
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Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
Symbol DDR2–800
DQ low impedance time from CK/CK tLZ.DQ
DQS/DQS low-impedance time from tLZ.DQS
CK / CK
MRS command to ODT update delay tMOD
Mode register set command cycle tMRD
time
OCD drive mode output delay
tOIT
DQ/DQS output hold time from DQS tQH
DQ hold skew factor
tQHS
Average periodic refresh Interval
tREFI
Auto-Refresh to Active/Auto-Refresh tRFC
command period
Precharge-All (4 banks) command tRP
period
Read preamble
Read postamble
Active to active command period for
1KB page size products
tRPRE
tRPST
tRRD
Active to active command period for tRRD
2KB page size products
Internal Read to Precharge command tRTP
delay
Write preamble
tWPRE
Write postamble
tWPST
Write recovery time
tWR
Internal write to read command delay tWTR
Exit power down to read command tXARD
Exit active power-down mode to read tXARDS
command (slow exit, lower power)
Exit precharge power-down to any tXP
valid command (other than NOP or
Deselect)
Exit self-refresh to a non-read
command
tXSNR
Exit self-refresh to read command
Write command to DQS associated
clock edges
tXSRD
WL
Min.
2 x tAC.MIN
tAC.MIN
Max.
tAC.MAX
tAC.MAX
0
12
2
—
0
12
tHP – tQHS —
—
300
—
7.8
—
3.9
105
—
tRP
—
0.9
1.1
0.4
0.6
7.5
—
10
—
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
8 – AL
—
2
—
tRFC +10
—
200
—
RL – 1
DDR2–667
Min.
2 x tAC.MIN
tAC.MIN
Max.
tAC.MAX
tAC.MAX
0
12
2
—
0
12
tHP – tQHS —
—
340
—
7.8
—
3.9
105
—
tRP
—
0.9
1.1
0.4
0.6
7.5
—
10
—
7.5
—
0.35
—
0.4
0.6
15
—
7.5
—
2
—
7 – AL
—
2
—
tRFC +10
—
200
—
RL–1
Unit
Note2)3)5
)6)7)8)
ps
9)22)
ps
9)22)
ns
35)
nCK
ns
35)
ps
26)
ps
27)
µs
28)29)
µs
28)30)
ns
31)
ns
tCK.AVG
tCK.AVG
ns
32)33)
32)34)
35)
ns
35)
ns
35)
tCK.AVG
tCK.AVG
ns
ns
35)
35)36)
nCK
nCK
nCK
ns
35)
nCK
nCK
1) For details and notes see the relevant Qimonda component data sheet
2) VDDQ = 1.8 V ± 0.1V; VDD = 1.8 V ± 0.1 V.
3) Timing that is not specified is illegal and after such an event, in order to guarantee proper operation, the DRAM must be powered down
and then restarted through the specified initialization sequence before normal operation can continue.
Rev. 1.13, 2007-10
17
08212006-PKYN-2H1B
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