HYS64T32X00EDL_1 Datasheet, PDF (16/79 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules

Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
2) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross. The DQS / DQS, RDQS / RDQS,
input reference level is the crosspoint when in differential strobe mode
3) Inputs are not recognized as valid until V_REF stabilizes. During the period before V_REF stabilizes, CKE = 0.2 x V_DDQ
4) The output timing reference voltage level is V_TT.
5) t_RAS.MAX is calculated from the maximum amount of time a DDR2 device can operate without a refresh command which is equal to 9 x t_REFI.
6) Product released after 01-08-2007 will support t_RAS = 40 ns for all DDR2 speed sort.
3.3.2
Component AC Timing Parameters
Parameter
TABLE 14
DRAM Component Timing Parameter by Speed Grade - DDR2–800 and DDR2–667
Symbol DDR2–800
Min.
Max.
DDR2–667
Min.
Max.
Unit
Note²⁾³⁾⁵
)6)7)8)
CAS to CAS command delay
Average clock high pulse width
Average clock period
CKE minimum pulse width ( high and
low pulse width)
t_CCD
t_CH.AVG
t_CK.AVG
t_CKE
Average clock low pulse width
Auto-Precharge write recovery +
precharge time
t_CL.AVG
t_DAL
Minimum time clocks remain ON after t_DELAY
CKE asynchronously drops LOW
DQ and DM input hold time
t_DH.BASE
DQ and DM input pulse width for each t_DIPW
input
DQS input high pulse width
DQS input low pulse width
DQS-DQ skew for DQS & associated
DQ signals
t_DQSH
t_DQSL
t_DQSQ
DQS latching rising transition to
associated clock edges
t_DQSS
DQ and DM input setup time
DQS falling edge hold time from CK
DQS falling edge to CK setup time
CK half pulse width
t_DS.BASE
t_DSH
t_DSS
t_HP
Data-out high-impedance time from t_HZ
CK / CK
Address and control input hold time
Control & address input pulse width
for each input
t_IH.BASE
t_IPW
Address and control input setup time t_IS.BASE
2
0.48
2500
3
—
0.52
8000
—
0.48
WR + t_nRP
0.52
—
t_IS + t_{CK .AVG} ––
+ t_IH
125
––
0.35
—
0.35
—
0.35
—
—
200
– 0.25
+ 0.25
50
––
0.2
—
0.2
—
Min(t_CH.ABS,
t_CL.ABS)
—
__
t_AC.MAX
250
—
0.6
—
175
—
2
0.48
3000
3
—
0.52
8000
—
0.48
WR + t_nRP
0.52
—
t_IS +
––
t_{CK .AVG} + t_IH
175
––
0.35
—
0.35
—
0.35
—
—
240
– 0.25
+ 0.25
100
0.2
0.2
Min(t_CH.ABS,
t_CL.ABS)
—
––
—
—
__
t_AC.MAX
275
—
0.6
—
200
—
nCK
t_CK.AVG
ps
nCK
10)11)
12)
t_CK.AVG
nCK
10)11)
13)14)
ns
ps
t_CK.AVG
15)19)20)
t_CK.AVG
t_CK.AVG
ps
16)
t ¹⁷⁾
CK.AVG
ps
t_CK.AVG
t_CK.AVG
ps
18)19)20)
17)
17)
21)
ps
9)22)
ps
23)25)
t_CK.AVG
ps
24)25)
Rev. 1.13, 2007-10
16
08212006-PKYN-2H1B