HYS64T32X00EDL_1 Datasheet, PDF (21/79 Pages) Qimonda AG – 200-Pin SO-DIMM DDR2 SDRAM Modules

Internet Data Sheet
HYS64T[32/64/128]xxxEDL–[25F/…/3.7](–)B2
Small Outlined DDR2 SDRAM Modules
Parameter
TABLE 15
DRAM Component Timing Parameter by Speed Grade - DDR2–533
Symbol
DDR2–533
Min.
Max.
Unit
Notes^2)3)4)5)6)
7)
CAS A to CAS B command period
t_CCD
CK, CK high-level width
t_CH
CKE minimum high and low pulse width t_CKE
CK, CK low-level width
t_CL
Auto-Precharge write recovery +
t_DAL
precharge time
Minimum time clocks remain ON after
CKE asynchronously drops LOW
t_DELAY
DQ and DM input hold time (differential t_DH.BASE
data strobe)
DQ and DM input hold time (single ended t_DH1.BASE
data strobe)
DQ and DM input pulse width (each
input)
t_DIPW
DQS input HIGH pulse width (write cycle) t_DQSH
DQS input LOW pulse width (write cycle) t_DQSL
DQS-DQ skew (for DQS & associated
DQ signals)
t_DQSQ
Write command to 1st DQS latching
transition
t_DQSS
DQ and DM input setup time (differential t_DS.BASE
data strobe)
DQ and DM input setup time (single
ended data strobe)
t_DS1.BASE
DQS falling edge hold time from CK
t_DSH
(write cycle)
DQS falling edge to CK setup time (write t_DSS
cycle)
Four Activate Window period
t_FAW
Four Activate Window period
t_FAW
Clock half period
t_HP
Data-out high-impedance time from CK / t_HZ
CK
Address and control input hold time
Address and control input pulse width
(each input)
t_IH.BASE
t_IPW
Address and control input setup time
DQ low-impedance time from CK / CK
DQS low-impedance from CK / CK
MRS command to ODT update delay
t_IS.BASE
t_LZ(DQ)
t_LZ(DQS)
t_MOD
2
0.45
3
0.45
WR + t_RP
t_IS + t_CK + t_IH
225
—
0.55
—
0.55
—
––
––
–25
—
0.35
—
0.35
—
0.35
—
—
300
– 0.25
+ 0.25
100
—
–25
—
0.2
—
0.2
—
37.5
50
MIN. (t_CL, t_CH)
—
375
0.6
—
—
t_AC.MAX
—
—
250
2 × t_AC.MIN
t_AC.MIN
0
—
t_AC.MAX
t_AC.MAX
12
t_CK
t_CK
t_CK
t_CK
t_CK
8)
ns
9)
ps
10)
ps
11)
t_CK
t_CK
t_CK
ps
11)
t_CK
ps
11)
ps
11)
t_CK
t_CK
ns
ns
13)
12)
ps
13)
ps
11)
t_CK
ps
11)
ps
14)
ps
14)
ns
Rev. 1.13, 2007-10
21
08212006-PKYN-2H1B