HYB39S128400F Datasheet, PDF (2/21 Pages) Qimonda AG – 128-MBit Synchronous DRAM

Data Sheet
HY[B/I]39S128[40/80/16][0/7]F[E/T](L)
128-MBit Synchronous DRAM
HYB39S128400F[E/T](L), HY[B/I]39S128800F[E/T](L), HY[B/I]39S128160F[E/T](L)
Revision History: 2007-10, Rev. 1.32
Page
Subjects (major changes since last revision)
All
Adapted Internet Version
23
Corrected number of refresh cycles
Previous Revision: 2007-06, Rev. 1.31
13
Corrected operation command "Power Down / Clock suspend ...” in truth table
15
Corrected text to "After the mode register is set a NOP command is required"
19
Corrected text to "One clock delay is required for mode entry and exit", chapter 3.5
19
Corrected the line "Input Capacitances: CK" in table 10, chapter 4
22
Corrected tCK MIN in table 14
22
Corrected CLE setup time in table 14
Previous Revision: 2007-03, Rev. 1.30
15
Corrected mode register definition
21
IDD for low power option 0.8 mA
22
“Transition time” replaced by “Transition Time of Clock (Rise and Fall)”
4
Added HYI39S128800FT-7, HYI39S128800FE-7, HYI39S128160FT-7, HYI39S128160FE-7 and
HYB39S128407FE-7
Previous Revision: 2006-10, Rev. 1.20
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qag_techdoc_rev400 / 3.2 QAG / 2006-08-01
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