HYS64D32020 Datasheet, PDF (19/34 Pages) Qimonda AG – 200-Pin Small Outline Dual-In-Line Memory Modules

Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
10) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
11) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge. A valid transition
is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were previously in progress on the
bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress, DQS could be HIGH, LOW, or transitioning from
HIGH to LOW at this time, depending on t_DQSS.
12) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
Rev. 1.31, 2006-09
19
03292006-VN6D-DETI