HYS64D32020 Datasheet, PDF (18/34 Pages) Qimonda AG – 200-Pin Small Outline Dual-In-Line Memory Modules

Internet Data Sheet
HYS64D[32/16]0x0[G/H]DL–[5/6]–C
Small-Outline DDR SDRAM Modules
Parameter
Symbol –5
DDR400B
–6
DDR333
Unit Note¹⁾/ Test
Condition
Address and control input setup time t_IS
Min.
0.6
Max.
—
Min.
0.75
Max.
—
ns Fast slew rate
3)4)5)6)8)
0.7
—
0.8
—
ns Slow slew rate
3)4)5)6)8)
Data-out low-impedance time from t_LZ
–0.7
CK/CK
+0.7 –0.7
+0.7
ns
2)3)4)5)7)
Mode register set command cycle t_MRD
2
time
—
2
—
t_CK
2)3)4)5)
DQ/DQS output hold time
Data hold skew factor
Active to Autoprecharge delay
Active to Precharge command
Active to Active/Auto-refresh
command period
t_QH
t_QHS
t_RAP
t_RAS
t_RC
t_HP – t_QH
—
t_RCD
40
55
—
+0.50
—
70E+3
—
t_HP – t_QHS
—
t_RCD
42
60
—
ns
+0.55 ns
—
ns
70E+3 ns
—
ns
2)3)4)5)
TSOPII ^2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
Active to Read or Write delay
t_RCD
15
Average Periodic Refresh Interval t_REFI
—
Auto-refresh to Active/Auto-refresh t_RFC
65
command period
—
18
7.8
—
—
72
—
ns
2)3)4)5)
7.8
µs
2)3)4)5)10)
—
ns
2)3)4)5)
Precharge command period
Read preamble
Read postamble
Active bank A to Active bank B
command
t_RP
t_RPRE
t_RPST
t_RRD
15
0.9
0.40
10
—
18
1.1
0.9
0.60 0.40
—
12
—
1.1
0.60
—
ns
2)3)4)5)
t_CK
2)3)4)5)
t_CK
2)3)4)5)
ns
2)3)4)5)
Write preamble
t_WPRE
Write preamble setup time
t_WPRES
Write postamble
t_WPST
Write recovery time
t_WR
Internal write to read command delay t_WTR
Exit self-refresh to non-read
command
t_XSNR
0.25
0
0.40
15
2
75
—
0.25
—
0
0.60 0.40
—
15
—
1
—
75
—
—
0.60
—
—
—
t_CK
2)3)4)5)
ns
2)3)4)5)11)
t_CK
2)3)4)5)12)
ns
2)3)4)5)
t_CK
2)3)4)5)
ns
2)3)4)5)
Exit self-refresh to read command t_XSRD
200
—
200
—
t_CK
2)3)4)5)
1) 0 °C ≤ T_A ≤ 70 °C; V_DDQ = 2.5 V ± 0.2 V, V_DD = +2.5 V ± 0.2 V (DDR333); V_DDQ = 2.6 V ± 0.1 V, V_DD = +2.6 V ± 0.1 V (DDR400)
2) Input slew rate ≥Σ 1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference level for signals
other than CK/CK, is V_REF. CK/CK slew rate are ≥ 1.0 V/ns.
4) Inputs are not recognized as valid until V_REF stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is V_TT.
6) For each of the terms, if not already an integer, round to the next highest integer. t_CK is equal to the actual system clock cycle time.
7) t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions. These parameters are not referred to a specific
voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
8) Fast slew rate ≥ 1.0 V/ns, slow slew rate ≥ 0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns, measured
between V_IH(ac) and V_IL(ac).
9) These parameters guarantee device timing, but they are not necessarily tested on each device.
Rev. 1.31, 2006-09
18
03292006-VN6D-DETI