HYS72T1G042ER Datasheet, PDF (18/31 Pages) Qimonda AG – 240-Pin Dual Die Registered DDR2 SDRAM Modules

Internet Data Sheet
HYS72T1G042ER–5–B
Registerd DDR2 SDRAM Module
9) The clock frequency is allowed to change during self-refresh mode or precharge power-down mode.
10) For timing definition, refer to the Component data sheet.
11) Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output Slew Rate
mis-match between DQS / DQS and associated DQ in any given cycle.
12) MIN (t_CL, t_CH) refers to the smaller of the actual clock low time and the actual clock high time as provided to the device (i.e. this value can
be greater than the minimum specification limits for t_CL and t_CH).
13) The t_HZ, t_RPST and t_LZ, t_RPRE parameters are referenced to a specific voltage level, which specify when the device output is no longer driving
(t_HZ, t_RPST), or begins driving (t_LZ, t_RPRE). t_HZ and t_LZ transitions occur in the same access time windows as valid data transitions.These
parameters are verified by design and characterization, but not subject to production test.
14) The Auto-Refresh command interval has be reduced to 3.9 µs when operating the DDR2 DRAM in a temperature range between 85 °C
and 95 °C.
15) 0 °C≤ T_CASE ≤ 85 °C
16) 85 °C < T_CASE ≤ 95 °C
17) A maximum of eight Auto-Refresh commands can be posted to any given DDR2 SDRAM device.
18) The t_RRD timing parameter depends on the page size of the DRAM organization. See Table 2 “Ordering Information for RoHS
Compliant Products” on Page 4.
19) The maximum limit for the t_WPST parameter is not a device limit. The device operates with a greater value for this parameter, but system
performance (bus turnaround) degrades accordingly.
20) Minimum t_WTR is two clocks when operating the DDR2-SDRAM at frequencies ≤ 200 ΜΗz.
21) User can choose two different active power-down modes for additional power saving via MRS address bit A12. In “standard active power-
down mode” (MR, A12 = “0”) a fast power-down exit timing t_XARD can be used. In “low active power-down mode” (MR, A12 =”1”) a slow
power-down exit timing t_XARDS has to be satisfied.
22) WR must be programmed to fulfill the minimum requirement for the t_WR timing parameter, where WR_MIN[cycles] = t_WR(ns)/t_CK(ns) rounded
up to the next integer value. t_DAL = WR + (t_RP/t_CK). For each of the terms, if not already an integer, round to the next highest integer. t_CK
refers to the application clock period. WR refers to the WR parameter stored in the MRS.
3.3.3
ODT AC Electrical Characteristics
Symbol
TABLE 14
ODT AC Electrical Characteristics and Operating Conditions for DDR2-400
Parameter / Condition
Values
Unit
Note
Min.
Max.
t_AOND
t_AON
ODT turn-on delay
ODT turn-on
2
t_AC.MIN
2
t_AC.MAX + 1 ns
t_CK
ns
1)
t_AONPD
ODT turn-on (Power-Down Modes)
t_AC.MIN + 2 ns 2 t_{CK +} t_AC.MAX + 1 ns
ns
t_AOFD
t_AOF
ODT turn-off delay
ODT turn-off
2.5
t_AC.MIN
2.5
t_AC.MAX + 0.6 ns
t_CK
ns
2)
t_AOFPD
ODT turn-off (Power-Down Modes)
t_AC.MIN + 2 ns 2.5 t_{CK +} t_AC.MAX + 1 ns ns
t_ANPD
ODT to Power Down Mode Entry Latency
3
—
t_CK
t_AXPD
ODT Power Down Exit Latency
8
—
t_CK
1) ODT turn on time min. is when the device leaves high impedance and ODT resistance begins to turn on. ODT turn on time max is when
the ODT resistance is fully on. Both are measure from t_AOND.
2) ODT turn off time min. is when the device starts to turn off ODT resistance. ODT turn off time max is when the bus is in high impedance.
Both are measured from t_AOFD.
Rev. 1.0, 2007-04
18
04242007-NQ2Z-YM3O