HYB18M512160BF-6 Datasheet, PDF (17/24 Pages) Qimonda AG – DRAMs for Mobile Applications 512-Mbit DDR Mobile-RAM RoHS compliant

3.3
Operating Currents
HY[B/E]18M512160BF
512-Mbit DDR Mobile-RAM
Electrical Characteristics
Table 14 Maximum Operating Currents^1)2)3)4)5)
Parameter & Test Conditions
Symbol Values Unit
- 6 - 7.5
Operating one bank active-precharge current:
I_DD0
70
50 mA
t_RC = t_RCmin; t_CK = t_CKmin; CKE is HIGH; CS is HIGH between valid commands; address inputs
are SWITCHING; data bus inputs are STABLE
Precharge power-down standby current:
all banks idle, CKE is LOW; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD2P 0.70 0.70 mA
Precharge power-down standby current with clock stop:
all banks idle, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control inputs
are SWITCHING; data bus inputs are STABLE
I_DD2PS
0.60
0.60 mA
Precharge non power-down standby current:
all banks idle, CKE is HIGH; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD2N
18
15 mA
Precharge non power-down standby current with clock stop:
all banks idle, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
I_DD2NS 1.5 1.5 mA
Active power-down standby current:
one bank active, CKE is LOW; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD3P
2
2 mA
Active power-down standby current with clock stop:
I_DD3PS 1.5
one bank active, CKE is LOW; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
1.5 mA
Active non power-down standby current:
one bank active, CKE is HIGH; CS is HIGH, t_CK = t_CKmin; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD3N
25
22 mA
Active non power-down standby current with clock stop:
I_DD3NS 2.5
one bank active, CKE is HIGH; CS is HIGH, CK = LOW, CK = HIGH; address and control
inputs are SWITCHING; data bus inputs are STABLE
2.5 mA
Operating burst read current:
one bank active; BL = 4; CL = 3; t_CK = t_CKmin; continuous read bursts;
I_OUT = 0 mA; address inputs are SWITCHING; 50% data change each burst transfer
Operating burst write current:
one bank active; BL = 4; t_CK = t_CKmin; continuous write bursts;
address inputs are SWITCHING; 50% data change each burst transfer
I_DD4R 105 75 mA
I_DD4W 110 75 mA
Auto-Refresh current:
t_RC = t_RFCmin; t_CK = t_CKmin; burst refresh; CKE is HIGH; address and control inputs are
SWITCHING; data bus inputs are STABLE
I_DD5 185 135 mA
Self refresh current:
CKE is LOW; CK = LOW, CK = HIGH; address and control inputs are STABLE; data bus
I_DD6 see Table 15 µA
inputs are STABLE
Deep Power Down current
I_DD8
1) 0 °C ≤ T_C ≤ 70 °C (comm.); -25 °C ≤ T_C ≤ 85 °C (ext.); V_DD = V_DDQ = 1.70 V - 1.90 V.
Recommended Operating Conditions unless otherwise noted
25⁶⁾
µA
2) IDD specifications are tested after the device is properly intialized and measured at 133 MHz for -7.5 and 166 MHz for -6
speed grade.
Internet Data Sheet
17
Rev.1.80, 2006-11
07092007-3E44-UTNM