PACE1754 Datasheet, PDF (4/20 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC)

PACE1754
AC ELECTRICAL CHARACTERISTICS^{1, 2}
(V_CC = 5V ± 10% Over Recommended Operating Conditions)
20 MHz
30MHz
40 MHz
Symbol
Parameter
Min Max Min Max Min Max
tEX RDY (RDYD)_V
Time from External Ready to
Ready Data Valid
16
14
12
tC (RDYD)_V
Time from Clock Read to
Ready Data Valid
28
22
16
tSTRBA_H (A)_V
Time from Strobe Address HIGH to
Address Bus Valid
29
21
19
tIBA_V (A)_V
Time from Information Bus Address to
Address Bus Valid
31
22
20
tFC (R)_L
Time from Falling Clock to
Read LOW
24
18
12
tSTRBD_H (R)_H
Time from Strobe Data HIGH to
Read HIGH
24
18
12
tSTRBD_L (W)_L
Time from Strobe Data LOW to
Write LOW
26
20
15
tSTRBD_H (W)_H
Time from Strobe Data HIGH to
Write HIGH
26
20
15
tIBD_IN (ME PA ER)_L
Time from Information Bus Data into
Memory Parity Error LOW
22
17
12
tIBA_IN (EX AD ER)
Time from Information Bus Address into
30
25
20
External Address Error
tSTRBD_L –
(STRT ROM)_V
tFC (IB OUT)_V
Time from Strobe Data LOW to
Start-up ROM Valid
Time from Falling Clock to
Information Bus Valid
26
20
15
30
25
25
tC (TIMER CLK)
Time from Rising Edge of Clock to
Timer Clock
30
25
20
tIB IN_V (IB16)
Time from Information Bus Data to
Parity Valid
25
20
18
tEXT AD (CLKB3)
Extended Address
Setup Time
10
10
10
tEX RDY1 (RDYD)_V
Time from External Ready Data to
Ready Data Valid
28
24
21
tFC (SCR EN)
Time from Falling Clock to SCR Enable;
30
24
24
Case Types T and X only
tSTRBD_H (SCR EN) Time from STRBD HIGH to SCR Enable;
30
24
24
Case Types T and X only
Notes:
1. 4.5V ≤ V_CC ≤ 5.5V, –55°C ≤ T_C ≤ +125°C. Unless otherwise specified, testing shall be conducted at worst-case conditions.
2. All measurements of delay times on active signals are related to the 1.5V levels.
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document # MICRO-5 REV C
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