PACE1754 Datasheet, PDF (12/20 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 40MHz CMOS PROCESSOR INTERFACE CIRCUIT (PIC)

PACE1754
PIN FUNCTIONS
Symbol
Name
CPU CLK
CPU Clock
STRBA
Strobe Address
STRBD
Strobe Data
TIMER CLK
MEMW
MEMR
IOW
IOR
INTA
SCR EN
Timer Clock
Memory Write Strobe
Memory Read Strobe
I/O Write Strobe
I/O Read Strobe
Interrupt Acknowledge
Strobe
System Configuration
STRB EN
Strobe Enable
IB₀ - IB₁₅
Information Bus (0:15)
IB₁₆
Information Bus (16)
A(0:1)/
EX AD(0:1),
A(2:15)
Address Bus (0:15)
M/IO
Memory I/O
Description
A single-phase input clock signal (0-40MHz, 40% to 60% duty cycle.)
An active HIGH input which latches the contents of IB(0:15) into the
address latches.
An active LOW input which is used for writing or reading data to or
from the device and also to produce the external memory and I/O
strobes.
A 100KHz output (fixed frequency) based on the programmed
operating frequency of the CPU clock.
An active LOW output produced in memory write cycles.
An active LOW output produced in memory read cycles.
An active LOW output produced in output write cycles.
An active LOW output produced in input read cycles.
An active LOW output produced after any interrupt, corresponding to
an output write to address 1000 (hex).
An active LOW output (in 64 pin only) produced any time an input
read from address 8410 (hex), read system configuration is
executed.
An active LOW input, enabling the active state of the address
outputs and the MEMR, MEMQ, IOR, and IOW outputs. When at a
logic "1" (if enabled by bits EST, EAD of the control register) it will
correspondingly enable the three-state state of the above signals.
A bi-directional time multiplexed bus. It is an input during the
address phase of any bus cycle and also during the data phase
when writing. It is an output during the data phase when reading
from the device.
A bi-directional line. It is an output during write cycles and an input
during read cycles. It is used to implement the parity function at the
system level.
An active HIGH output bus. Contains the address of the current bus
cycle as latched by the end of STRBA. In system configurations
including the MMU function, the only active lines during memory are
A(4:15). In this case, A(2:3) are high impedance (don't care) and
A(0:1) turn into inputs called Extended Addresses, EXT ADR (0:1).
In this case, these two lines supplied by the MMU, will be used to
operate the programmable ready generation during bus cycles.
An input qualifier indicating the nature of the current bus cycle.
Document # MICRO-5 REV C
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