PACE1750A Datasheet, PDF (14/24 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR

PACE1750A
SIGNAL DESCRIPTIONS (Continued)
BUS ARBITRATION
Mnemonic
Name
Description
BUS REQ
Bus request
An active LOW output that indicates the CPU requires the bus. It
becomes inactive when the CPU has acquired the bus and started the
bus cycle.
BUS GNT
Bus grant
An active LOW input from an external arbiter that indicates the CPU
currently has the highest priority bus request. If the bus is not used and
not locked, the CPU may begin a bus cycle, commencing with the next
CPU clock. A HIGH level will hold the CPU in Hi-Z state (Bz), three-
stating the IB bus status lines (D/I, R/W, M/IO), strobes (STRBA,
STRBD), and all the other lines that go three-state when this CPU does
not have the bus.
BUS BUSY
Bus busy
An active LOW, bidirectional signal used to establish the beginning and
end of a bus cycle. The trailing edge (LOW-to-HIGH transition) is used
for sampling bits into the fault register. It is three-state in bus cycles not
assigned to this CPU. However, the CPU monitors the BUS BUSY line
for latching non-CPU bus cycle faults into the fault register.
BUS LOCK
Bus lock
An active low, bi-directional signal used to lock the bus for successive
bus cycles. During non-locked bus cycles, the BUS LOCK signal mimics
the BUS BUSY signal. It is three-state during bus cycles not assigned to
the CPU. The following instructions will lock the bus: INCM, DECM, SB,
RB, TSB, SRM, STUB and STLB.
DISCRETE CONTROL
Mnemonic
Name
DMA EN
Direct memory
Access enable
NML PWRUP Normal power up
SNEW
TRIGO RST
Start new
Trigger-go reset
Description
An active HIGH output that indicates the DMA is enabled. It is
disabled when the CPU is initialized (reset) and can be enabled or
disabled under program control (I/O commands DMAE, DMAD).
An active HIGH output that is set when the CPU has successfully
completed the built-in self test in the initialization sequence. It can be
reset by the I/O command RNS.
An active HIGH output that indicates a new instruction is about to start
executing in the next cycle.
An active LOW discrete output. This signal can be pulsed low under
program control I/O address 400B (Hex) and is automatically pulsed
during processor initialization.
Document # MICRO-3 Rev. C
Page 14 of 24