PACE1750A Datasheet, PDF (11/24 Pages) Pyramid Semiconductor Corporation – SINGLE CHIP, 15MHz to 40MHz, CMOS 16-BIT PROCESSOR

BUS ACQUISITION
PACE1750A
Note:
A CPU contending for the BUS will assert the BUS REQ line, and will acquire it when BUS GNT is assserted and the BUS is not locked
(BUS LOCK is high).
SWITCHING TIME TEST CIRCUITS
Standard Output (Non-Three-State)
Three-State
Note:
All time measurements on active signals relate to the 1.5 volt level.
Parameter
t_PLZ
t_PHZ
t_PXL
t_PXH
V0
≥ 3V
0V
V_CC/2
V_CC/2
VMEA
0.5V
V_CC – 0.5V
1.5V
1.5V
Document # MICRO-3 Rev. C
Page 11 of 24