PT6332 Datasheet, PDF (24/37 Pages) Princeton Technology Corp – VFD Driver/Controller IC

VFD Driver/Controller IC
Tel: [phone]
Fax: [phone]
URL: http://www.princeton.com.tw
PT6332
BLOCK STATES DURING THE RESET PERIOD
(when /BLK is low)
• Divider and timing generator
These circuits are reset and their base clock is stopped.
• Dimmer timing generator
The circuit is reset and its operation is stopped.
• Digit and segment dividers
These circuits are reset and the display is turned off (SG1 to SG56 and GR1 to GR3 are set low).
• Key scan
The circuit is reset, its internal circuits are set to the initial state, and key scanning is disabled.
• Key buffer
The circuit is reset and all data is set to 0.
• Clock generator
The state (normal or sleep mode) of this block (the clock oscillator circuit) is determined after the
sleep control data (S0 to S1) is transferred.
• CCB interface, shift register, control register, latch, and multiplexer
The circuits are not reset so that serial data can be input during the reset period.
/BLK
VFL
VDD
V SS 1
V SS 2
OSCI
G ri d
D ri ve r
Tim in g
G e ner ato r
Di vi der
Clo ck
G e ner ato r
Block than are reset
PT6332 V1.0
D im me r
Tim in g
G e ner ato r
S egm ent Driver
57
M PX
17 1
La tch
Con tro l
R egiste r
16
57
S hift Reg ister
Key Buffer
C ommand
Inte rfa ce
K ey S ca n
- 24 -
February, 2006