PT6880 Datasheet, PDF (14/42 Pages) Princeton Technology Corp – OLED Driver/Controller IC

OLED Driver/Controller IC
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Preliminary
PT6880
The 11th line CGRAM data bits 0 to 4 must be set to "0". If any of the 11th line CGRAM
data bits 0 to 4 is set to "1", the corresponding display location will light up regardless of
the cursor position.
6. When the Character Code Bits 4 to 7 are set to "0", then the CGRAM Character Pattern is
selected. It must be noted that Character Code Bit -- 0 and 3 are not relevant and will not
have any effect on the character display. Because of this, the Character Pattern shown
above ( P ) can be displayed when the Character Code is 00H, 01H, 08H or 09H.
Timing Generation Circuit
The timing signals for the internal circuit operations (i.e. DDRAM, CGRAM, and CGROM) are generated
by the Timing Generation Circuit. The timing signals for the MPU internal operation and the RAM Read
for Display are generated separately in order to prevent one from interfering with the other. This means
that, for example, when the data is being written into the DDRAM, there will be no unwanted interference
such as flickering in areas other than the display area.
OLED Driver Circuit
PT6880 provides 16 Common Drivers and 40 Segment Driver Outputs. When a character font and the
number of lines to be displayed have been selected, the corresponding Common Drivers output the drive
waveform automatically. A non-selection waveform will be outputted by the rest of the Common Drivers.
Serial data transmission always begins with the display data character pattern corresponding to the last
Display Data RAM (DDRAM) Address. The serial data is latched when the display data character pattern
corresponding to the starting address enters the internal shift register. Thus, PT6880 drives from the head
display.
Cursor / Blink Control Circuit
The cursor or character blinking is generated by the Cursor / Blink Control Circuit.The cursor or the
blinking will appear with the digit located at the Display Data RAM (DDRAM) Address Set in the
Address Counter (AC).
AC6
AC5
AC4
AC3
AC2
AC1
AC0
Address Counter
0
0
0
1
0
0
0
CASE 1: FOR 1-LINE DISPLAY
Example: When the Address Counter (AC) is set to 08H, the cursor position is displayed at DDRAM
PT6880 pre 1.1
Page 14
Mar. 2002