PE97042 Datasheet, PDF(9/11 Page) Peregrine Semiconductor – 3.5 GHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

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PE97042 Datasheet, PDF (9/11 Pages) Peregrine Semiconductor – 3.5 GHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

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PE97042

Product Specification

Serial Interface Mode

Serial Interface Mode is selected by setting the

DMODE input âlowâ.

While the E_WR input is âlowâ, serial data (DATA

input), B0 to B19, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B0) first. The

contents from this buffer register are transferred

into the frequency control register on the rising

edge of S_WR according to the timing diagram

shown in Figure 9. This data controls the counters

as shown in Table 7.

While the E_WR input is âhighâ, serial data (DATA

input), B0 to B7, is clocked into a buffer register on

the rising edge of CLOCK, LSB (B0) first. The

contents from this buffer register are transferred

into the enhancement register on the falling edge

of E_WR according to the timing diagram shown

in Figure 9. After the falling edge of E_WR, the

data provides control bits as shown in Table 8.

These bits are active when the ENH input is âlowâ.

Direct Interface Mode

Direct Interface Mode is selected by setting

the DMODE input âhighâ. In this mode, the counter

values are set directly at external pins as shown in

Table 7 and Figure 2. All frequency control

possible to bypass the Ã·10/11 dual modulus

prescaler in Direct Mode).

Table 7. Frequency Register Programming

Interface

Mode

ENH

DMODE

Serial*

B10

B11

B12

B13

B14

B15

B16

B17

B18 B19

Direct

* Data is clocked serially on CLOCK rising edge while E_WR is âlowâ and transferred to frequency register on S_WR rising edge.

MSB (first in)

(last in) LSB

Table 8. Enhancement Register Programming

Interface

Mode

ENH

DMODE

Reserved*

fp output

Power

down

Counter

load

MSEL

output

fc output

Serial**

* Program to 0

* Data is clocked serially on CLOCK rising edge while E_WR is âlowâ and transferred to frequency register on S_WR rising edge.

MSB (first in)

(last in) LSB

Document No. 70-0236-05 â www.psemi.com

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