PE97042 Datasheet, PDF (5/11 Pages) Peregrine Semiconductor – 3.5 GHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

PE97042
Product Specification
Table 6. AC Characteristics: V_DD = 3.3 V, -40 °C < T_A < 85 °C, unless otherwise specified
Symbol
Parameter
Conditions
Min Typical
Control Interface and Latches (see Figures 1 and 9)
f_Clk
CLOCK Serial data clock frequency
(Note 1)
t_ClkH
CLOCK Serial clock HIGH time
30
t_ClkL
CLOCK Serial clock LOW time
30
t_DSU
DATA set-up time after CLOCK rising edge
10
t_DHLD
DATA hold time after CLOCK rising edge
10
t_PW
S_WR pulse width
30
t_CWR
CLOCK rising edge to S_WR rising edge.
30
t_CE
CLOCK falling edge to E_WR transition
30
t_WRC
S_WR falling edge to CLOCK rising edge.
30
t_EC
E_WR transition to CLOCK rising edge
30
t_MDO
MSEL data out delay after F_IN rising edge
C_L = 12 pf
Main Divider (Including Prescaler)⁴
P_Fin
Input level range
Main Divider (Prescaler Bypassed)⁴
External AC coupling
275 MHz ≤ Freq ≤ 3.2 GHz
-5
External AC coupling
3.2 GHz < Freq ≤ 3.5 GHz
0
3.15 V ≤ V_DD ≤ 3.45 V
Max
10
8
5
5
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
dBm
dBm
F_IN
P_Fin
Reference Divider
Operating frequency
Input level range
50
External AC coupling
-5
300
MHz
5
dBm
F_R
Operating frequency
(Note 3)
P_Fr
Reference input power²
Single-ended input
-2
Phase Detector
f_c
Comparison frequency
(Note 3)
SSB Phase Noise (F_in = 1.9 GHz, f_r = 20 MHz, f_c = 20 MHz, LBW = 50 kHz, V_DD = 3.3 V, Temp = 25 C)⁴
_N
Phase Noise
100 Hz Offset
_N
Phase Noise
1 kHz Offset
_N
Phase Noise
10 kHz Offset
SSB Phase Noise (F_in = 1.9 GHz, f_r = 20 MHz, f_c = 20 MHz, LBW = 50 kHz, V_DD = 3.0 V, Temp = 25 C)⁴
_N
Phase Noise
100 Hz Offset
_N
Phase Noise
1 kHz Offset
_N
Phase Noise
10 kHz Offset
-89
-95
-102
-87
-94
-101
100
MHz
10
dBm
50
MHz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Notes: 1. Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
2. CMOS logic levels can be used to drive the reference input. If the V_DD of the CMOS driver matches the V_DD of PLL IC, then the reference
input can be DC coupled. Otherwise, the reference input should be AC coupled.
3. Parameter is guaranteed through characterization only and is not tested.
4. Parameters below are not tested for die sales. These parameters are verified during the element evaluation.
Document No. 70-0236-05 │ www.psemi.com
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