PE97042 Datasheet, PDF (3/11 Pages) Peregrine Semiconductor – 3.5 GHz UltraCMOS Integer-N PLL Rad Hard for Space Applications

PE97042
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name Interface Mode
17
GND
Both
Type
CLOCK
Serial
18
M₆
Direct
19
M₇
Direct
20
M₈
Direct
21
A₀
Direct
22
D_MODE
Both
23
V_DD
Both
24
E_WR
Serial
A₁
Direct
25
A₂
Direct
26
A₃
Direct
Input
Input
Input
Input
Input
Input
(Note 1)
Input
Input
Input
Input
27
F_IN
Both
Input
Description
Ground
Clock input. Data is clocked serially into either the 20-bit primary register (E_WR
“low”) or the 8-bit enhancement register (E_WR “high”) on the rising edge of
CLOCK.
M Counter bit6
M Counter bit7
M Counter bit8 (MSB)
A Counter bit0
Selects direct interface mode (D_MODE = 1) or serial interface mode (D_MODE = 0)
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
Enhancement register write enable. While E_WR is “high”, DATA can be serially
clocked into the enhancement register on the rising edge of CLOCK.
A Counter bit1.
A Counter bit2
A Counter bit3 (MSB)
Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and terminated with a 50 Ω
resistor to ground.
28
F_IN
Both
29
GND
30
N/C
31
V_DD
Both
Both
32
D_OUT
Serial
33
V_DD
Both
34
N/C
35
GND
Both
36
PD_D
Both
37
PD_U
Both
38
V_DD
Both
39
C_EXT
40
GND
41
GND
42
F_R
43
ENH
44
LD
Both
Both
Both
Both
Both
Serial
Input
(Note 1)
Output
(Note 1)
Output
(Note 1)
Output
Input
Output
Output
Prescaler complementary input. A 22 pF bypass capacitor should be placed as
close as possible to this pin and be connected in series with a 50 Ω resistor to
ground.
Ground.
No connect.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
Data Out. The Main Counter output, R Counter output, or dual modulus prescaler
select (MSEL) can be routed to D_OUT through enhancement register programming.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
No connect.
Ground.
PD_D pulses down when f_p leads f_c.
PD_U pulses down when f_c leads f_p.
Power supply input. Input may range from 2.85 V to 3.45 V. Bypassing
recommended.
Logical “NAND” of PD_U and PD_D, passed through an on-chip, 2 kΩ series
resistor. Connecting C_EXT to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Ground
Ground
Reference frequency input
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
Lock detect output, the open-drain logical inversion of C_EXT. When the loop is
locked, LD is high impedance; otherwise LD is a logic low (“0”).
Notes 1. VDD pins 1, 11, 12, 23, 31, 33, 35, and 38 are connected by diodes and must be supplied with the same positive voltage level.
2. All digital input pins have 70 kΩ pull-up resistors to VDD.
Document No. 70-0236-05 │ www.psemi.com
©2007-2011 Peregrine Semiconductor Corp. All rights reserved.
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