PE9701 Datasheet, PDF (6/13 Pages) Peregrine Semiconductor Corp. – 3000 MHz UltraCMOS™ Integer-N PLL Rad Hard for Space Applications

PE9701
Product Specification
Table 6. AC Characteristics: V_DD = 3.0 V, -40° C < T_A < 85° C, unless otherwise specified
Symbol
Parameter
Conditions
Min
Max
Units
Control Interface and Latches (see Figures 4, 5, 6)
fClk
Serial data clock frequency
(Note 1)
10
MHz
tClkH
Serial clock HIGH time
30
ns
tClkL
Serial clock LOW time
tDSU
Sdata hold time after Sclk rising edge, D[7:0] set-up time to
M1_WR, M2_WR, A_WR, E_WR rising edge
tDHLD
Sdata hold time after Sclk rising edge, D[7:0] hold time to
M1_WR, M2_WR, A_WR, E_WR rising edge
30
ns
10
ns
10
ns
tPW
S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width
tCWR
Sclk rising edge to S_WR rising edge. S_WR, M1_WR,
M2_WR, A_WR falling edge to Hop_WR rising edge
tCE
Sclk falling edge to E_WR transition
tWRC
S_WR falling edge to Sclk rising edge. Hop_WR falling
edge to S_WR, M1_WR, M2_WR, A_WR rising edge
tEC
E_WR transition to Sclk rising edge
30
ns
30
ns
30
ns
30
ns
30
ns
tMDO
MSEL data out delay after Fin rising edge
CL = 12 pf
8
ns
Main Divider (Prescaler Enabled)
Fin
Operating frequency
500
3000
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
Main Divider (Prescaler Bypassed)
Fin
Operating frequency
50
300
MHz
PFin
Input level range
External AC coupling
-5
5
dBm
Reference Divider
fr
Operating frequency
(Note 3)
100
MHz
Pfr
Reference input power (Note 2)
Single-ended input
-2
dBm
Phase Detector
fc
Comparison frequency
(Note 3)
20
MHz
Note 1:
Note 2:
Note 3:
Fclk is verified during the functional pattern test. Serial programming sections of the functional pattern are clocked at 10 MHz to verify Fclk
specification.
CMOS logic levels can be used to drive reference input if DC coupled. Voltage input needs to be a minimum of 0.5 Vp-p.
Parameter is guaranteed through characterization only, and is not tested.
©2003-2006 Peregrine Semiconductor Corp. All rights reserved.
Page 6 of 13
Document No. 70-0035-02 │ UltraCMOS™ RFIC Solutions