PE99151DIE Datasheet, PDF (5/15 Pages) Peregrine Semiconductor – Hi-Rel 2A DC-DC Converter

PE99151 DIE
Product Specification
Table 3. Pin Coordinates and Descriptions
(continued)
Pin
No.
Pin Name
X
Y
Description
25
EAINP
–1343.9
1068.3
Error Amplifier (+) Input,
Load Feedback
1.000V Reference output,
26
VREF
–1343.9
1266.9
Loop to AAINP. Additional
Low Pass Filtering May be
Necessary
27
GND
–1343.9 1437.25 Ground
28
AGND
–1142.8 1283.2 Bandgap ground
29
RSET
–1142.8
–1283.2
Resistor to Set Reference
Current
30
SScap
–944.2
1283.2
Resistor to Set Reference
Current
31
SYNCOb
–944.2
–1283.2
Loop-Through Comple-
ment Output
32
SYNC
–745.6
1283.2
Loop-Through Comple-
ment Output
33
PGOOD –745.6 –1283.2 Power Good Flag Output
34
SDb
–547 1283.2 Shutdown (L)/enable input
35
RSEL_SDAT
–547
–1283.2
Reference Resistor
Selection
36
TEST
–348.4 1283.2 Ground
37
SCLK
–348.4 –1283.2 Ground
38
V_IN
602.5 1000 Input Power Supply
39
V_IN
1102.5
0 Input Power Supply
40
V_IN
602.5 –1000 Input Power Supply
Table 4. Operating Ranges
Symbol
Parameter/Condition
V_IN Power supply voltage
T_A
Operating temperature range
(ambient)
Min Max Unit
4.6 6.0
V
–55 +125 °C
Table 5. Absolute Maximum Ratings
Symbol
Parameter/Condition
Min Max Unit
V_IN Power supply voltage
T_j
Operating temperature range
(junction)
–0.5 6.5
V
–55 +145 ^oC
T_ST Storage temperature range
–65 +150 ^oC
I_I
DC into any signal input
–10 10 mA
I_O
DC into any signal output
–50 50 mA
I_P
DC into any single power pin
–2 2
A
Exceeding absolute maximum ratings may cause
permanent damage. Operation between maximum
operating range and absolute maximum for
extended periods may reduce reliability.
Table 6. Electrostatic Discharge (ESD) Ratings
Model
Parameter/Condition
Min Max Unit
HBM* V_ESD All pins
1000
V
Note: * Human Body Model ESD Voltage (HBM, MIL_STD 883 Method 3015.7).
Electrostatic Discharge (ESD) Precautions
When handling this UltraCMOS device, observe the
same precautions that you would use with other
ESD-sensitive devices. Although this device
contains circuitry to protect it from damage due to
ESD, precautions should be taken to avoid
exceeding the specified rating.
Latch-Up Immunity
Unlike conventional CMOS devices, UltraCMOS
devices are immune to latch-up.
ELDRS
The UltraCMOS process does not exhibit enhanced
low-dose-rate sensitivity (ELDRS) since bipolar
minority carrier elements are not used.
Document No. DOC-50370-6 │ www.e2v-us.com
©2012–2015 Peregrine Semiconductor Corp. All rights reserved.
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