PE99151DIE Datasheet, PDF (11/15 Pages) Peregrine Semiconductor – Hi-Rel 2A DC-DC Converter

PE99151 DIE
Product Specification
The DC resistance of the Inductor will primarily impact
efficiency. For optimal efficiency, the inductor DC
resistance should be selected to be on the order of
magnitude of the R_ON of the high side switch and low side
switch. Calculation of the efficiency impact will be
discussed in the efficiency section of the Design Guide. A
smaller DC resistance will improve efficiency but will likely
impact PCB area, a subject not addressed in this Design
Guide.
Output Capacitor Selection
The output Capacitor works in tandem with the output
Inductor to filter the Inductor ripple current and to source
and sink current to meet the load demand during a load
step. The output Capacitor is implemented as a network of
parallel capacitors covering low, mid, and high frequency
operation. The capacitor Equivalent Series Resistance
(ESR) and Equivalent Series Inductance (ESL) have a
direct impact on the output voltage ripple, output voltage
droop under transient loading, and loop stability. Ceramic
X7R dielectric capacitors are recommended for their
thermal and electrical properties, along with their size and
cost.
Figure 7. Output Capacitor Selection
DCR
Inductor
Vout
SRF Cap
ESR ¹
ESR ²
ESR ³
Load
ESL ¹
ESL ²
ESL ³
Cout ¹
Low Freq
Cout ²
Mid Freq
Cout ³
High Freq
The output voltage droop should be empirically determined
to satisfy the application load step response requirements.
During a transient step in the load current, the output
voltage will initially experience an IR drop of ∆I_LOAD × ESR.
If the output capacitor bank is too large, the IR drop is
minimized but the V_OUT recovery time is longer. If the
output capacitor bank is too small, the IR drop is increased
but the V_OUT recovery time is shorter.
The output voltage ripple should be chosen to meet the
application requirements and tradeoff with the physical
size of the capacitor bank. The output voltage ripple
waveform can be estimated by taking the inverse Fourier
transform of the product of the Fourier transform of the
input signal and the frequency domain transfer function of
the network in Figure 9. (The input to the transfer function
can be approximated as an ideal square wave with period
of F_SW, amplitude of V_IN and a duty ratio of V_OUT / V_IN.)
If a SPICE simulation tool is available, the above
estimation can be done by placing the above mentioned
square wave at the input of the filter network and solving
for the output waveform.
Additionally, the total output capacitance and load
resistance set the dominant pole of the voltage mode
control loop. Voltage mode loop stability is described in the
"Voltage Control Loop Compensation Network Design"
section.
In addition to playing a role in stability and output voltage
ripple, the output capacitor bank must be able to absorb
the inductor ripple current. The inductor peak-to-peak
ripple current, calculated as ∆IL in the inductor selection
section, will be absorbed by the capacitor bank. Note that
the RMS current through the output cap can be calculated
as ∆IL/√3 since inductor ripple current waveform is
triangular. The frequency range of capacitors absorbing
the ripple current must be rated to handle this ripple
current.
The PE99151 reference design features three output
capacitors (Cout1, Cout2, and Cout3) that have been chosen
to blend total capacitance, ESR, and ESL to meet the ripple,
droop, and stability requirements over frequency.
Input Capacitor Selection
The input capacitor network sources the trapezoidal
current wave through the source terminal of the high side
switch. Therefore, the RMS current handling and maximum
voltage rating are the main considerations in selecting the
input capacitors.
Neglecting the small (as compared with the load) Inductor
ripple current and assuming that the input capacitor
sources all of the ripple current, the RMS current through
the input capacitor can be calculated as
I_RMS–CIN = I_{LOAD (max)} × √ [D × (1–D)]
In addition to sourcing the trapezoidal current wave
through the high side switch, the input bypass capacitors
absorb the high frequency components of the switching
power supply preventing conducted EMI from reaching the
up stream supply. As such, the input bypass capacitor
SRF should be on the order of 10x higher than the
switching frequency of the buck regulator. Additional high
frequency capacitors may be added to further attenuate
the high frequency conducted EMI.
Like the output capacitors, Ceramic X7R dielectric
capacitors are recommended with the added benefit that
the X7R capacitors have very low DC voltage de-rating.
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