PE99151DIE Datasheet, PDF (14/15 Pages) Peregrine Semiconductor – Hi-Rel 2A DC-DC Converter

PE99151 DIE
Product Specification
One requirement of the voltage control loop stability
analysis and design is to maintain significant attenuation at
the switching frequency of the converter. If this
requirement is not met, the switching noise can enter the
control loop and loop stability will be lost. To ensure
sufficient attenuation at the switching frequency, a unity
gain cross over frequency one decade below the switching
frequency is recommended. Additional margin may be
desired depending on the application requirements.
The pole created by the load and the output capacitor is
dependent on load current. The load current can vary,
likely all the way down to zero load current. When this
happens the output pole frequency falls arbitrarily low. It is
clear that this highly variable pole will not be sufficient to
set a dominant pole in the loop to ensure stability.
The recommended compensation technique is a combined
pole-zero compensation network. The zero is set to cancel
the variable load pole at minimum load so that the load
pole does not affect phase margin of the system when the
pole location is at it's minimum value, possibly even in the
bandwidth of the control loop. With the load pole canceled
by the additional zero, the added pole in the compensation
network acts as a stable dominant pole. This dominant
pole location can be selected for both attenuation of the
F_SW switching noise and for the required phase margin and
loop bandwidth.
With this compensation technique, the zero location is
calculated as 1 / (2πR_CC_C). R_C and C_C should be selected
to cancel the load pole at minimum load.
If the compensation network resistor is selected to be
much less than the output impedance R_OUT of the error
operational transconductance amplifier (OTA), the
dominant pole location can then be approximated as
1 / (2πR_OUTC_C). At first glance this may seem to make the
dominant pole location dependent on the loosely controlled
error amp output impedance. However, as the error amp
output impedance drops, the DC gain of the system and
the dominant pole location reduce together. The result is
that the unity gain cross over frequency (set by the
dominant pole) is independent of OTA output impedance
variation over process and temperature.
A compensation network design spreadsheet is available in
the PE9915x Design Tool.
Figure 10. PE99151 Control Loops
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