PE97632 Datasheet, PDF (4/15 Pages) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE97632
Product Specification
Pin No. Pin Name
Valid Mode
Type
Description
46
V_DD
47
F_in
48
F_in
49 GND
Both
Both
50 CEXT
51 LD
Both
Both
52
D_OUT
Both
53
V_DD
54 GND
55 ^PD_D
Both
56 NC
57 ^PD_U
Both
Both
58 GND
59
V_DD
60
V_DD
61 GND
62 f_r
63
V_DD
Both
64
V_DD
GND
65 Enh
Both
66 NC
Both
67 MS2_SEL Both
(Note 1)
Input
Prescaler V_DD.
Prescaler input from the VCO, 3.5 GHz max frequency. A 22 pF coupling capacitor should
be placed as close as possible to this pin and terminated with a 50 Ω resistor to ground.
Input
Prescaler complementary input. A 22pF bypass capacitor should be placed as close as
possible to this pin and be connected in series with a 50 Ω resistor to ground.
Downbond Ground
Output
Logical “NAND” of PD_U and PD_D terminated through an on chip, 2 kΩ series resistor.
Connecting Cext to an external capacitor will low pass filter the input to the inverting
amplifier used for driving LD.
Output
Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high
impedance, otherwise LD is a logic low (“0”).
Output Data out function, enabled in enhancement mode.
(Note 1) Output driver/V_DD.
Downbond Ground
Output ^{PD_D pulses down when f}p ^{leads f}c^.
(Note 3) No Connect
Output ^{PD_U pulses down when f}c ^{leads f}p^.
Downbond Ground
(Note 1) Output driver/V_DD.
(Note 1) Phase detector V_DD.
Downbond Ground
Input Reference frequency input.
(Note 1) Reference V_DD.
(Note 1) Digital core V_DD.
Downbond Ground
Input Enhancement mode. When asserted low (“0”), enhancement register bits are functional.
(Note 3) No Connect
Input MASH 1-1 select. “High” selects MASH 1-1 mode. “Low” selects the MASH 1-1-1 mode.
68 RND_SEL Both
Input
K register LSB toggle enable. “1” enables the toggling of LSB. This is equivalent to having
an additional bit for the LSB of K register. The frequency offset as a result of enabling this
bit is the phase detector comparison frequency / 2¹⁹.
Notes 1. All VDD pins are connected by diodes and must be supplied with the same positive voltage level.
2. All digital input pins have 70 kΩ pull-down resistors to ground.
3. No Connect pins can be left open or floating.
©2006-2011 Peregrine Semiconductor Corp. All rights reserved.
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Document No. 70-0205-07 │ UltraCMOS™ RFIC Solutions