PE97632 Datasheet, PDF (11/15 Pages) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE97632
Product Specification
A consequence of the upper limit on A is that:
In Integer-N mode, F_in must be ≥ 90 x (f_r / (R+1)) to
obtain contiguous channels.
In MASH-1-1 mode, F_in must be ≥ 91 x (f_r / (R+1)) to
obtain contiguous channels.
In MASH-1-1-1 mode, F_in must be ≥ 93 x (f_r / (R+1)) to
obtain contiguous channels.
The A counter can accept values as high as 15, but in
typical operation it will cycle from 0 to 9 in increments
of M. Programming the M counter with the minimum
allowed value of “1” will result in a minimum M counter
divide ratio of “2”.
Prescaler Bypass Mode (*)
Setting the frequency control register bit Pre_en
“high” allows F_in to bypass the ÷10/11 prescaler. In this
mode, the prescaler and A counter are powered down,
and the input VCO frequency is divided by the M
counter directly. The following equation relates F_in to
the reference frequency f_r:
F_in = (M + 1) x (f_r / (R+1))
(5)
where 1≤ M≤ 511
(*) Only Integer-N mode
In frequency bypass mode, neither A counter or K
counter is used. Therefore, only Integer-N operation is
possible.
Reference Counter
The reference counter chain divides the reference
frequency f_r down to the phase detector comparison
frequency f_c.
The output frequency of the 6-bit R Counter is related
to the reference frequency by the following equation:
f_c = f_r / (R + 1)
(6)
where 0≤ R≤ 63
Note that programming R with “0” will pass the
reference frequency (f_r) directly to the phase detector.
Document No. 70-0205-07 │ www.psemi.com
©2006-2011 Peregrine Semiconductor Corp. All rights reserved.
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