PE97632 Datasheet, PDF (10/15 Pages) List of Unclassifed Manufacturers – 3.2 GHz Delta-Sigma modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE97632
Product Specification
Main Counter Chain
Normal Operating Mode
The PE97632 can be operated in Integer-N mode or
either Fractional-N mode. The main counter chain
divides the RF input frequency (Fin) by an integer or
fractional number derived from the values in the “M”,
“A” counters and the DSM input word K. Setting the
Pre_en control bit “high” operates the part only in
Integer-N mode. In addition, even if Pre_en is "low" if
K=0 the part is operated in Integer-N mode.
The Fractional-N modes use a MASH (Multi-stAge
noise SHaping) decimation structure. The MS2_SEL
pin sets the MASH mode.
MASH-1-1 mode is a 2nd order fractional dithering
using four (2²) N values: N-1, N, N+1, N+2.
MASH 1-1-1 mode is a 3rd order fractional dithering
using eight (2³) N values: N-3, N-2, N-1, N, N+1, N+2,
N+3, N+4.
Using the part in MASH-1-1 or MASH-1-1-1 mode will
yield spurs at frequency offsets equal to
Fspur =
±[(2K + RND_SEL)/(2¹⁹)] x f_c
±[1-(2K + RND_SEL)/(2¹⁹)] x f_c
1 ≤K ≤ 131072 (1)
131073 ≤ K ≤ 262143
where f_c is the Phase Detector (comparison) frequency,
K is the DSM input word, and RND_SEL is the K
register LSB toggle enable.
MASH-1-1-1 mode reduces these spurs for an increase
in the phase noise and a decrease in the number of
valid programming frequencies.
The 18-bit DSM accumulator fixes the fractional value
of N from the ratio K/2¹⁸ and the frequency step size as
f_c/2¹⁸. There is an additional bit in the DSM that acts
like an extra bit (19th bit). This bit is enabled by
asserting the pin RND_SEL to “high”. Enabling this bit
has the benefit of reducing the spur levels. This is
especially beneficial for large K-counter values that do
not use any lower bits, causing an accumulation of
random values in these bits and additional spurs.
The side effect of asserting RND_SEL is that a small
frequency offset will occur. This positive frequency
offset is calculated with the following equation:
f_offset = (f_r / (R + 1)) / 2¹⁹
(2)
All of the following equations do not take into account
this frequency offset. If this offset is important to a
specific frequency plan, it should be taken into account
accordingly.
In addition, K-counter values at the minimum,
maximum and midpoint have higher spur levels that
may not be reduced by enabling RND_SEL. If the PD
comparison frequency is slightly shifted, the K value
can be experimented with to move away from the
suboptimal values.
During normal operation, the output from the main
counter chain (f_p) is related to the VCO frequency (F_in)
by the following equation:
f_p = F_in / N
(3)
where
N = 10 x (M+1) + A + (2K + RND_SEL)/2¹⁹
A≤ M + 1, 1≤ M≤ 511
When the loop is locked, F_in is related to the reference
frequency (f_r) by the following equation:
F_in = N x (f_r / (R+1))
(4)
where
N = 10 x (M+1) + A + (2K + RND_SEL)/2¹⁹
A≤ M + 1, 1≤ M≤ 511
Document No. 70-0205-07 │ www.psemi.com
©2006-2011 Peregrine Semiconductor Corp. All rights reserved.
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