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PE97632DIE Datasheet, PDF (3/16 Pages) Peregrine Semiconductor – 3.5 GHz Delta-Sigma Modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications
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PE97632 DIE
Product Specification
Table 1. Pad Descriptions (Cont.)
Pad No.
Pad
Name
Valid
Mode
Type
18
K7
Direct
Input
19
K8
Direct
Input
20
K9
Direct
Input
21
K10
Direct
Input
22
K11
Direct
Input
23
K12
Direct
Input
24
K13
Direct
Input
25
K14
Direct
Input
26
K15
Direct
Input
27
K16
Direct
Input
28
K17
Direct
Input
29
VDD
Note 1
30
VDD
Note 1
31
GND
Downbond
32
GND
Downbond
33
M0
Direct
Input
34
M1
Direct
Input
35
M2
Direct
Input
36
M3
Direct
Input
M4
Direct
Input
37
S_WR
Serial
Input
M5
Direct
Input
38
SDATA
Serial
Input
M6
Direct
Input
39
SCLK
Serial
Input
40
M7
Direct
Input
41
M8
Direct
Input
42
A0
Direct
Input
A1
Direct
Input
43
E_WR
Serial
Input
44
A2
Direct
Input
45
A3
Direct
Input
46
DIRECT
Both
Input
47
Pre_en
Direct
Input
48
VDD
Note 1
49
GND
Downbond
50
GND
Downbond
Description
K counter bit7.
K counter bit8.
K counter bit9.
K counter bit10.
K counter bit11.
K counter bit12.
K counter bit13.
K counter bit14.
K counter bit15.
K counter bit16.
K counter bit17 (MSB).
Digital core VDD.
Digital core VDD.
Ground.
Ground.
M counter bit0 (LSB).
M counter bit1.
M counter bit2
M counter bit3.
M counter bit4.
Serial load enable input. While S_WR is “low”, SDATA can be serially clocked. Primary register
data are transferred to the secondary register on S_WR rising edge.
M counter bit5.
Binary serial data input. Input data entered MSB first.
M counter bit6.
Serial clock input. SDATA is clocked serially into the 21-bit primary register (E_WR “low”) or
the 8-bit enhancement register (E_WR “high”) on the rising edge of SCLK.
M counter bit7.
M counter bit8 (MSB).
A counter bit0 (LSB).
A counter bit1.
Enhancement register write enable. While E_WR is “high”, SDATA can be serially clocked into
the enhancement register on the rising edge of SCLK.
A counter bit2.
A counter bit3 (MSB).
Direct mode select. “High” enables direct mode. “Low” enables serial mode.
Prescaler enable, active “low”. When “high”, FIN bypasses the prescaler.
Digital core VDD.
Ground.
Ground.
Document No. DOC-01626-3 │ www.psemi.com
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