PE97632DIE Datasheet, PDF (12/16 Pages) Peregrine Semiconductor – 3.5 GHz Delta-Sigma Modulated Fractional-N Frequency Synthesizer for Low Phase Noise Applications

PE97632 DIE
Product Specification
Phase Detector
The phase detector is triggered by rising edges
from the main counter (f_p) and the reference coun-
ter (f_c). It has two outputs, namely PD_U, and
PD_D. If the divided VCO leads the divided refer-
ence in phase or frequency (f_p leads f_c), PD_D
pulses “low”. If the divided reference leads the di-
vided VCO in phase or frequency (f_c leads f_p),
PD_U pulses “low”. The width of either pulse is
directly proportional to phase offset between the
two input signals, f_p and f_c.
For the UP and DOWN mode, PD_U and PD_D
drive an active loop filter which controls the VCO
tune voltage. The phase detector gain is equal to
V_DD / 2п.
PD_U pulses cause an increase in VCO frequency
and PD_D pulses cause a decrease in VCO fre-
quency, for a positive kV VCO.
A lock detect output, LD is also provided, via the
pin C_EXT. C_EXT is the logical “NAND” of PD_U and
PD_D waveforms, which is driven through a series
2 kΩ resistor. Connecting C_EXT to an external
shunt capacitor provides low pass filtering of this
signal. C_EXT also drives the input of an internal in-
verting comparator with an open drain output.
Thus LD is an “AND” function of PD_U and PD_D.
Figure 5. Typical Phase Noise
A typical phase noise plot is shown below. “Trace 1” is the smoothed average and “Trace 2” is the raw data.
Test conditions: MASH 1-1 mode, FOUT = 1.9204 GHz, FCOMPARISON = 20 MHz, VDD = 3.3V, temp = +25 °C,
loop bandwidth = 50 kHz.
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Document No. DOC-01626-3 │ UltraCMOS^® RFIC Solutions