PE97240 Datasheet, PDF (3/21 Pages) Peregrine Semiconductor – Radiation Tolerant UltraCMOS Integer-N Frequency Synthesizer for Low Phase Noise Applications

PE97240
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. Pin Name
Interface Mode
Type
Description
17
Direct
18
A0
Direct
Direct
Input
Input
Select “High” enables Direct Mode. Select “Low” enables Serial Mode.
A counter bit0
A1
19
E_WR
20
A2
21
V_DD
22
Pre_en
23
Pre_5/6_Sel
24
V_DD
Direct
Serial
Direct
Both
Direct
Direct
Both
Input
Input
Input
Note 1
Input
Input
Note 1
A counter bit1
Enhancement register write enable. While E_WR is “high”, SDATA can be serially
clocked into the enhancement register on the rising edge of SCLK.
A counter bit2
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Prescaler enable, active “low”. When “high”, F_IN bypasses the prescaler.
5/6 modulus select, active “High.” When “Low,” 10/11 modulus selected.
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
25
F_IN
26
F_IN
27
GND
28
D_OUT
29
C_EXT
30
LD
31
V_DD
32
PD_D
33
PD_U
34
V_DD
35
V_DD
36
GND
37
F_R
38
V_DD
39
ENH
40
R0
41
R1
42
R2
43
R3
Both
Both
Both
Serial
Both
Both
Both
Both
Both
Both
Both
Both
Both
Both
Serial
Direct
Direct
Direct
Direct
Input
Input
Output
Output
Output
Note 1
Output
Output
Note 1
Note 1
Input
Note 1
Input
Input
Input
Input
Input
Prescaler complementary input. A 22 pF bypass capacitor should be placed as close
as possible to this pin and be connected in series with a 50Ω resistor to ground.
Prescaler input from the VCO, 5.0 GHz max frequency. A 22 pF coupling capacitor
should be placed as close as possible to this pin and be connected in shunt to a
50Ω resistor to ground.
Ground
Data Out. The MSEL signal and the raw prescaler output are available on Dout
through enhancement register programming.
Logical “NAND” of PD_D and PD_U terminated through an on chip, 2 kΩ series
resistor. Connecting Cext to an external capacitor will low pass filter the input to the
inverting amplifier used for driving LD.
Lock detect and open drain logical inversion of C_EXT. When the loop is in lock, LD is
high impedance, otherwise LD is a logic low (“0”).
Power supply input. Input may range from 2.6V to 2.8V. Bypassing recommended.
PD_D is pulse down when f_p leads f_c
PD_U is pulse down when f_c leads f_p
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Ground
Reference frequency input
Power supply input. Input may range from 2.6–2.8V. Bypassing recommended.
Enhancement mode. When asserted low (“0”), enhancement register bits are
functional.
R counter bit0
R counter bit1
R counter bit2
R counter bit3
44
GND
Both
Ground
Notes: 1. VDD pins 1, 10, 21, 24, 31, 34, 35 and 38 are connected by diodes and must be supplied with the same positive voltage level.
2. All digital input pins have 70 kΩ pull-down resistors to ground.
Document No. DOC-15214-7 │ www.e2v-us.com
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