PM4388 Datasheet, PDF (73/284 Pages) PMC-Sierra, Inc – Octal T1 Framer

DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
FBITBYP:
The FBITBYP bit allows the frame synchronization bit in the egress stream,
ED[x], to bypass the generation through the XBAS and be re-inserted into
the appropriate position in the digital output stream. When FBITBYP is set to
logic 1, the input frame synchronization bit is re-inserted into the output data
stream. When FBITBYP is set to logic 0, the XBAS is allowed to generate
the output frame synchronization bits.
CRCBYP:
The CRCBYP bit allows the framing bit corresponding to the CRC-6 bit
position in the egress stream, ED[x], to bypass the generation through the
XBAS and be re-inserted into the appropriate position in the digital output
stream. When CRCBYP is set to logic 1, the input CRC-6 bit is re-inserted
into the output data stream. When CRCBYP is set to logic 0, the XBAS is
allowed to generate the output CRC-6 bits.
FDLBYP:
The FDLBYP bit allows the framing bit corresponding to the facility data link
bit position in the egress data stream, ED[x], to bypass the generation
through the XBAS and be re-inserted into the appropriate position in the
digital output stream. When FDLBYP is set to logic 1, the input FDL bit is re-
inserted into the output data stream. When FDLBYP is set to logic 0, the
XBAS is allowed to generate the output FDL bit.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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