PM4388 Datasheet, PDF (228/284 Pages) PMC-Sierra, Inc – Octal T1 Framer

DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns
and underruns.
TDPR Interrupt Routine:
Upon assertion of INTB, the source of the interrupt must first be identified by
reading the Interrupt ID register and Interrupt Source registers. Once the source
of the interrupt has been identified as TDPR, then the following procedure should
be carried out:
1. Read the TDPR Interrupt Status register.
2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has
been corrupted and needs to be retransmitted. When the UDRI bit transitions
to logic 1, one Abort sequence and continuous flags will be transmitted. The
TDPR FIFO is held in reset state. To reenable the TDPR FIFO and to clear
the underrun, the TDPR Interrupt Status/UDR Clear register should be written
with any value.
3. If OVRI=1, then the FIFO has overflowed. The packet which the last byte
written into the FIFO belongs to has been corrupted and must be
retransmitted. Other packets in the FIFO are not affected. Either a timer can
be used to determine when sufficient bytes are available in the FIFO or the
user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is
at the lower threshold limit. The next write to the TDPR Transmit Data register
should contain the first byte of the next packet to be transmitted.
If the FIFO overflows on the packet currently being transmitted (packet is
greater than 128 bytes long), the OVRI bit is set, an Abort signal is scheduled
to be transmitted, the FIFO is emptied, and then flags are continuously sent
until there is data to be transmitted. The FIFO is held in reset until a write to
the TDPR Transmit Data register occurs. This write contains the first byte of
the next packet to be transmitted.
4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can
be written. When in this state, either a timer can be used to determine when
sufficient bytes are available in the FIFO or the user can wait until the LFILLI
interrupt is set, indicating that the FIFO depth is at the lower threshold limit.
If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state
earlier, but has since emptied out some of its data bytes and now has space
available in its FIFO for more data.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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