PM4388 Datasheet, PDF (127/284 Pages) PMC-Sierra, Inc – Octal T1 Framer

DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
When the NxDS0 mode is active, IDLE_DS0 also controls the generation of
ECLK[x]. When IDLE_DS0 is a logic 0, data is inserted from the egress
interface during that channel, and eight clock pulses are generated on
ECLK[x]. When IDLE_DS0 is a logic 1, an IDLE code byte is inserted, and
ECLK[x] is suppressed for the duration of that channel.
DMW:
When the DMW bit is set to a logic 1, the digital milliwatt pattern replaces the
ED[x] input data for the duration of that channel.
TEST:
When the TEST bit is set to a logic 1, channel data from the ED[x] input is
either overwritten with a test pattern from the PRGD block or is routed to the
PRGD block and compared against an expected test pattern. The
RXPATGEN bit in the Pattern Generator/Detector Positioning/Control register
determines whether the egress data is overwritten or compared as shown in
the following table:
TEST
0
1
1
RXPATGEN Description
X
Channel data is not included in test pattern
1
Channel data is routed to PRGD and compared
against expected test pattern
0
Channel data is overwritten with PRGD test pattern
All the channels that are routed to the PRGD are concatenated and treated
as a continuous stream in which pseudorandom or repetitive sequences are
searched for. Similarly, all channels set to be overwritten with PRGD test
pattern data are treated such that if the channels are subsequently extracted
and concatenated, the PRBS or repetitive sequence appears in the
concatenated stream. Pattern generation/detection can be enabled to work
on only the first 7 bits of a channel (for Nx56 kbps fractional T1) using the
Nx56k_DET and Nx56k_GEN bits in the Pattern Generator/Detector
Positioning/Control register (Reg. 00FH, 08FH, 10FH, 18FH, 20FH, 28FH,
30FH, 38FH). THe PRGD can also be enabled to work on the entire DS1,
including framing bits, using the UNF_GEN and UNF_DET bits in the Pattern
Generator/Detector Positioning/Control register.
LOOP:
The LOOP bit enables the DS0 loopback. When the LOOP bit is set to a logic
1, egress data is overwritten with the corresponding channel data from the
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