PM4388 Datasheet, PDF (117/284 Pages) PMC-Sierra, Inc – Octal T1 Framer

DATA SHEET
PMC-960840
ISSUE 5
PM4388 TOCTL
OCTAL T1 FRAMER
Registers 02DH, 0ADH, 12DH, 1ADH, 22DH, 2ADH, 32DH, 3ADH: ALMI
Interrupt Enable
Bit
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Type
R/W
R/W
R/W
R/W
R/W
Function
Unused
Unused
Unused
FASTD
ACCEL
YELE
REDE
AISE
Default
X
X
X
0
0
0
0
0
These registers select which of the three CFA's can generate an interrupt when
their logic state changes and enables the "fast" deassertion mode of operation.
FASTD:
The FASTD bit enables the "fast" deassertion of Red and AIS alarms. When
FASTD is set to a logic 1, deassertion of Red alarm occurs within 120 ms of
going in frame. Deassertion of AIS alarm occurs within 180 ms of either
detecting a 60 ms interval containing 127 or more zeros, or going in frame.
When FASTD is set to a logic 0, Red and AIS alarm deassertion times remain
as defined in the ALMI description.
ACCEL:
The ACCEL bit is used for production test purposes only. THE ACCEL BIT
MUST BE PROGRAMMED TO LOGIC 0 FOR NORMAL OPERATION.
YELE,REDE,AISE:
A logic 1 in the enable bit positions (YELE, REDE, AISE) enables a state
change in the corresponding CFA to generate an interrupt; a logic 0 in the
enable bit positions disables any state changes to generate an interrupt. The
enable bits are independent; any combination of Yellow, Red, and AIS CFA's
can be enabled to generate an interrupt.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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