PM5351 Datasheet, PDF (66/393 Pages) PMC-Sierra, Inc – Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device

S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
SATURN USER NETWORK INTERFACE (155-TETRA)
Pin Name
A[10]/TRS
RSTB
ALE
INTB
Type Pin
No.
Input A11
Input B10
pull-up
Input C11
pull-up
Output C10
Open-
drain
Function
The test register select (TRS) signal selects
between normal and test mode register accesses.
TRS is high during test mode register accesses,
and is low during normal mode register accesses.
The active-low reset (RSTB) signal provides an
asynchronous S/UNI-TETRA reset. RSTB is a
Schmitt triggered input with an integral pull-up
resistor.
The address latch enable (ALE) is active-high and
latches the address bus A[7:0] when low. When
ALE is high, the internal address latches are
transparent. It allows the S/UNI-TETRA to interface
to a multiplexed address/data bus. ALE has an
integral pull-up resistor.
The active-low interrupt (INTB) signal goes low
when a S/UNI-TETRA interrupt source is active and
that source is unmasked. The S/UNI-TETRA may
be enabled to report many alarms or events via
interrupts.
Examples of interrupt sources are loss of signal
(LOS), loss of frame (LOF), line AIS, line remote
defect indication (LRDI) detect, loss of pointer
(LOP), path AIS, path remote defect indication
detect and others.
INTB is tristated when the interrupt is acknowledged
via an appropriate register access. INTB is an open
drain output.
9.5 JTAG Test Access Port (TAP) Signals
Pin Name
TCK
Type Pin
No.
Input B8
Function
The test clock (TCK) signal provides timing for test
operations that are carried out using the IEEE
P1149.1 test access port.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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