PM5351 Datasheet, PDF (287/393 Pages) PMC-Sierra, Inc – Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device

S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
SATURN USER NETWORK INTERFACE (155-TETRA)
Register 0xCE: TXFP Transmit FIFO Error Aborted Frame Counter (LSB)
Bit Type Function
Bit 7 R TFERABF[7]
Bit 6 R TFERABF[6]
Bit 5 R TFERABF[5]
Bit 4 R TFERABF[4]
Bit 3 R TFERABF[3]
Bit 2 R TFERABF[2]
Bit 1 R TFERABF[1]
Bit 0 R TFERABF[0]
Default
X
X
X
X
X
X
X
X
Register 0xCF: TXFP Transmit FIFO Error Aborted Frame Counter (MSB)
Bit Type Function
Bit 7 R TFERABF[15]
Bit 6 R TFERABF[14]
Bit 5 R TFERABF[13]
Bit 4 R TFERABF[12]
Bit 3 R TFERABF[11]
Bit 2 R TFERABF[10]
Bit 1 R TFERABF[9]
Bit 0 R TFERABF[8]
Default
X
X
X
X
X
X
X
X
TFERABF[15:0]:
The TFERABF[15:0] bits indicate the number of FIFO error aborted POS
frames read from the transmit FIFO and inserted into the transmission stream
during the last accumulation interval. FIFO errors are caused when the FIFO
runs empty and the last byte read was not an end of packet or also when the
FIFO overruns and corrupts the EOP and SOP sequence. This is considered
a system error and should not occur when the system works normally. This
counter added to the Transmit User Aborted counter should account for all
aborted packets being sent on the line.
A write to any one of the TXFP-50 Transmit FIFO Error Aborted Frame
Counter registers loads the registers with the current counter value and resets
the internal 16 bit counter to 1 or 0. The counter reset value is dependent on
if there was a count event during the transfer of the count to these registers.
The counter should be polled every second to avoid saturating. The contents
of these registers are valid three TCLK cycles after a transfer is triggered.
Using the TIP feature by writing to the Channel Reset and Monitoring Register
(Register 0x05) will also update the counters.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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