PM5351 Datasheet, PDF (23/393 Pages) PMC-Sierra, Inc – Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device

S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
1.3 The Receive ATM Processor
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
SATURN USER NETWORK INTERFACE (155-TETRA)
• Extracts ATM cells from the received STS-3c (STM-1) synchronous payload
envelope using ATM cell delineation.
• Provides ATM cell payload de-scrambling.
• Performs header check sequence (HCS) error detection and correction, and
idle/unassigned cell filtering.
• Detects Out of Cell Delineation (OCD) and Loss of Cell Delineation (LCD).
• Counts number of received cells, idle cells, errored cells and dropped cells.
• Provides a synchronous 8-bit wide, four cell FIFO buffer.
1.4 The Receive POS Processor
• Generic design that supports packet based link layer protocols, like PPP,
HDLC and Frame Relay.
• Performs self synchronous POS data de-scrambling on SPE payload (x⁴³+1
polynomial).
• Performs flag sequence detection and terminates the received POS frames.
• Performs frame check sequence (FCS) validation. The POS processor
supports the validation of both CRC-CCITT and CRC-32 frame check
sequences.
• Performs Control Escape de-stuffing.
• Checks for packet abort sequence.
• Checks for octet aligned packet lengths and for minimum and maximum
packet lengths. Automatically deletes short packets (software configurable),
and marks those exceeding the maximum length as errored.
• Provides a synchronous 256 byte FIFO buffer accessed through a 16-bit data
bus on the POS-PHY System Interface.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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