PM5351 Datasheet, PDF (152/393 Pages) PMC-Sierra, Inc – Quad 155 Mbit/s ATM and Packet Over SONET/SDH Physical Layer Device

S/UNI-TETRA
DATASHEET
PMC-1971240
ISSUE 7
PMC-Sierra, Inc.
PM5351 S/UNI-TETRA
SATURN USER NETWORK INTERFACE (155-TETRA)
LRDIDET:
The LRDIDET bit determines the Line LRDI detection algorithm. When
LRDIDET is set to logic one, Line LRDI is declared when a 110 binary pattern
is detected in bits 6,7 and 8 of the K2 byte for three consecutive frames.
When LRDIDET is set to logic zero, Line LRDI is declared when a 110 binary
pattern is detected in bits 6,7 and 8 of the K2 byte for five consecutive frames.
AISDET:
The AISDET bit determines the Line AIS detection algorithm. When AISDET is
set to logic one, Line AIS is declared when a 111 binary pattern is detected in
bits 6,7 and 8 of the K2 byte for three consecutive frames. When AISDET is
set to logic zero, Line AIS is declared when a 111 binary pattern is detected in
bits 6,7 and 8 of the K2 byte for five consecutive frames.
ALLONES:
The ALLONES bit controls automatically forcing the SONET frame passed to
downstream blocks to logical all-ones whenever LAIS is detected. When
ALLONES is set to logic one, the SONET frame is forced to logic one
immediately when the LAIS alarm is declared. When LAIS is removed, the
received byte is immediately returned to carrying data. When ALLONES is
set to logic zero, the received byte carries the data regardless of the state of
LAIS.
BIPWORD:
The BIPWORD bit controls the accumulation of B2 errors. When BIPWORD
is logic one, the B2 error event counter is incremented only once per frame
whenever one or more B2 bit errors occur during that frame. When
BIPWORD is logic zero, the B2 error event counter is incremented for each
B2 bit error that occurs during that frame (the counter can be incremented up
to 24 times per frame).
Reserved:
The reserved bits must be programmed to logic zero for proper operation.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE
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