PM3351 Datasheet, PDF (260/268 Pages) PMC-Sierra, Inc – Single-Port 10/100 Mbit/s Ethernet Switch

DATA SHEET
PMC-970113
GPO23
GPO24
GO_ACK
GO_DPI
ISSUE 3
pulse
pulse
GPO25
GO_TXMCFRAME
pulse
MDIO outputs:
GPO26
GPO27
O_MDC
O_MDIO
GPO28
OE_MDIO
level
level
level
Switch Processor testing flips:
GPO29
RINT
level
GPO30
GPO31
ASSERT_ALARM1
ASSERT_ALARM2
level
level
PM3351 ELAN 1X100
SINGLE PORT FAST ETHERNET SWITCH
this flip will initiate the transfer handshake channel to do
an acknowledge counter increment
this flip sets a valid status bit in the DPI functional block
(DMA transfer channel) that indicates that the data
descriptor pointer in the RemDD is to be read across the
PCI expansion bus.
this flip sets a valid status bit in the TX_FIFO module that
indicates that a MAC Control frame should be transmit
(the implicit assumption is that the Switch Processor will
have written the correct frame contents to the Mac
Control frame ram prior to doing the GO_TXMCFRAME
flip).
these flips are used to control the MII
management interface pins: MDC and MDIO.
the level of this GPO line corresponds to the TTL logic
level on the MDC pin.
the level of this GPO line corresponds to the TTL logic
level driven by the PM3351 on the MDIO pin if the output
enable, OE_MDIO, is set (1).
MDIO output enable. If set (1) then the MDIO tristate
output buffer is enabled and the MDIO pin is driven to the
value of the O_MDIO GPO line.
these flips are used for test purposes.
RINT is a mask-able interrupt source for the INT_ pin on
the PM3351. If GPO29 is set (1) and the RINTMSK bit is
set in HCTRL, then the INT_ pin will be asserted (a TTL
logic low).
See description of RINT in Host Interface Status (HSTAT)
and Control (HCTRL) registers for additional details.
if set (1), the ALARM1 interrupt line will be asserted.
if set (1), the ALARM2 interrupt line will be asserted.
Coprocessor Test Conditions
The Switch Processor has 16 coprocessor conditions. From a programmer’s standpoint
they are not much different than the GPI inputs except that they are tested by using
different instructions (BCOP and BNCOP).
Coprocessor #
Cop0:
HW Name
LINK_IDLE
Cop1:
ANY_RXFRAME_INT
Description
set (1) if both the Link transmit and receive channels are
idle. This test condition is not required for switching
applications and is mapped to a cop_condition bit for
observability.
set (1) if either link receive interrupt line is set.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 254