PM3351 Datasheet, PDF (247/268 Pages) PMC-Sierra, Inc – Single-Port 10/100 Mbit/s Ethernet Switch

DATA SHEET
PMC-970113
ISSUE 3
PM3351 ELAN 1X100
SINGLE PORT FAST ETHERNET SWITCH
TXLATECOL:
late collision occurred during transmit. Valid when the collision interrupt is
asserted.
LT_TXLONG:
Link transmitting a frame having a size greater than the value of the
MAX_SIZE Link control register. Valid if TFRAME is asserted. This bit is
latched in the TXF_DSIZE register (which is valid when the TX_DONE
interrupt is asserted).
TFRAME:
transmitting frame on the MII interface.
TXLATEZONE:
this bit is set (1) if a frame is being transmit and the frame is in the late
collision zone (see Link control register LATE_COL).
TX_ENABLE:
transmit enable flow control bit (for observability).
TX_READY:
transmit enable flow control bit (for observability).
LINKRFRAME:
internal framing signal used by Link receiver to indicate to the DMA functional
block that a receive frame is in the LRF FIFO.
LRF_HAS_LASTWORD:
internal status signal- set (1) when the LRF FIFO has the last word of a
received frame.
RECEIVING:
the Link RX state machine is in a state corresponding to frame reception.
RX_READY_S:
the RX FIFO (on the MII interface) is non-empty.
LR_CTRL_FRAME:
receive frame status: a frame is being received having an Ethernet
Length/Type field of the same value as the ETYPE Link control register.
Status signal latched and held in DMSTAT control register.
LR_FIFO_OVRUN:
receive frame status: a FIFO over-run has occured in the Link receiver during
reception of this frame. Status signal latched and held in DMSTAT control
register.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 241