PM3351 Datasheet, PDF (121/268 Pages) PMC-Sierra, Inc – Single-Port 10/100 Mbit/s Ethernet Switch

DATA SHEET
PMC-970113
ISSUE 3
PM3351 ELAN 1X100
SINGLE PORT FAST ETHERNET SWITCH
If bilateral and uniform exchanges of frames are required in the system, then it is
obvious that at most eight devices (one for each pair of request/acknowledge counters)
can be supported. The following table shows, as an example, a three-device system
with devices numbered from 0 through 2, and identifies the request and acknowledge
counters that are incremented when a frame is transferred from any source device to
any destination device:
Src=chip #0
Src=chip #1
Src=chip #2
Dest = chip #0
N/A
Req ID = 1
Req ID = 2
N/A
Ack ID = 0
Ack ID = 0
Dest = chip #1
Req ID = 0
N/A
Req ID = 2
Ack ID = 1
N/A
Ack ID = 1
Dest = chip #2
Req ID = 0
Req ID = 1
N/A
Ack ID = 2
Ack ID = 2
N/A
In the table above, "Req" refers to the index of the request counter, and "Ack" refers to
the index of the acknowledge counter. Note that the request counter is always
incremented in the destination device, and the acknowledge counter is always
incremented in the source device. The index of the chip making the request or
returning the acknowledge can be obtained by simply inspecting the index of the
incremented counter.
An inspection of the table above will reveal that the indices of the request and
acknowledge counters that are incremented by any particular chip are always the same.
Thus, for example, chip #1 will always increment request counter #1 in any other device
when acting as a source of data, and will always increment acknowledge counter #1 in
another device when acting as a destination and acknowledging the receipt of data.
The foregoing has dealt with the use and configuration of the hardware communication
means, i.e., the request and acknowledge counter banks. The situation for the actual
data transfer is substantially simpler, as the ELAN 1x100 hardware and firmware place
no restrictions on the PCI addresses from which data copies may be done. Once a
particular request has been mapped to a specific source chip via the request counter
index by any external device, the 32-bit PCI address from which the data transfer must
be performed is defined by the 32-bit RemDD field of the expansion port descriptor
assigned to track transfers from that chip. Thus the only hard limitation on the number
of devices that may be supported by an ELAN system is set by the number of request
and acknowledge counters that are implemented in the ELAN 1x100 and ELAN 8x10
chips.
It should be noted that the assignments of counter indices to devices (as well as the
association of devices with actual PCI addresses) is performed statically at initialization
time by the boot image executed by every ELAN device.
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS’ INTERNAL USE 115